Showing papers in "Solid-state Electronics in 2017"

Improve the performance of CZTSSe solar cells by applying a SnS BSF layer

Abstract: In this study, the CZTSSe (Cu2ZnSn(S,Se)4) solar cells, with Al/ZnO:Al/ZnO (i)/CdS/CZTSSe/Mo structure, have been simulated. The simulation results have been compared and validated with real experimental results. Next, suggestions for improving the performance of CZTSSe solar cell have been provided. A SnS layer has been used as back surface field (BSF) layer. Different physical parameters of SnS layer are investigated, and the optimum values are selected. It has been found that by inserting a BSF layer with optimum parameters, the efficiency of CZTSSe solar cell increases from 12.3% to 17.25% due to enhancement of both short-circuit current density (Jsc) and open circuit voltage (Voc). For this optimized cell structure, the maximum Jsc = 37.37 mA/cm2, Voc = 0.605 V, and fill factor = 76.28% are obtained under 1.5 AM illumination.

A deterministic guide for material and mode dependence of on-chip electro-optic modulator performance

Abstract: Electro-optic modulation is a key function in optical data communication and possible future optical computing engines. The performance of modulators intricately depends on the interaction between the actively modulated material and the propagating waveguide mode. While high-performing modulators were demonstrated before, the approaches were taken as ad-hoc. Here we show the first systematic investigation to incorporate a holistic analysis for high-performance and ultra-compact electro-optic modulators on-chip. We show that intricate interplay between active modulation material and optical mode plays a key role in the device operation. Based on physical tradeoffs such as index modulation, loss, optical confinement factors and slow-light effects, we find that bias-material-mode regions exist where high phase modulation and high loss (absorption) modulation is found. This work paves the way for a holistic design rule of electro-optic modulators for on-chip integration.

Pt nanoparticles functionalized 3D SnO2 nanoflowers for gas sensor application

Abstract: 3D SnO2 nanoflowers (NFs) assembled by rod-like nanostructures were synthesized by a facile hydrothermal method only using simple and inexpensive SnCl4·5H2O and NaOH as the starting materials, without using any surfactants or templates. The as-synthesized 3D SnO2 NFs were further functionalized by Pt nanoparticles (NPs) by a simple ammonia precipitate method, and the derived Pt NP-functionalized 3D SnO2 NFs were further investigated for gas sensor application using ethanol as a probe gas. Obtained results showed that the Pt NP-functionalized 3D SnO2 NF sensor exhibited much higher response in comparison with pure SnO2 sensor, altogether with short response/recovery times and good reproducibility. The enhanced gas sensing performances could be attributed to spill-over effect of Pt NPs for promoting gas sensing reactions, the synergic electronic interaction between Pt NPs and SnO2 support, the high surface-to-volume ratio and good electron mobility of the 1D SnO2 nanorod units, and unique 3D hierarchical flower-like nanostructures. It is also expected that the as-prepared 3D SnO2 NFs and Pt NP-functionalized product can be used in other fields such as optoelectronic devices, Li-ion battery and dye sensitized solar cells.

Design and fabrication of a low insertion loss capacitive RF MEMS switch with novel micro-structures for actuation

Abstract: In this paper, we have developed an electrostatic driven capacitive RF MEMS switch. The actuation voltage is applied to the actuation electrodes, and the DC voltage is isolated from the signal line and RF signals. Actuation area and capacitance area are separated. Thanks to this structure, both low actuation voltage and low up-state capacitance are achieved. The switch can be integrated in RF systems without additional circuits to isolate the DC voltage, so the system is simplified. The proposed switch is fabricated and tested. The insertion loss and isolation of the fabricated switch are 0.29 dB and 20.5 dB at 35 GHz, respectively. The actuation voltage is 18.3 V.

A review of the Z 2 -FET 1T-DRAM memory: Operation mechanisms and key parameters

Abstract: The band-modulation and sharp-switching mechanisms in Z2-FET device operated as a capacitorless 1T-DRAM memory are reviewed. The main parameters that govern the memory performance are discussed based on detailed experiments and simulations. This 1T-DRAM memory does not suffer from super-coupling effect and can be integrated in sub-10 nm thick SOI films. It offers low leakage current, high current margin, long retention, low operating voltage especially for programming, and high speed. The Z2-FET is suitable for embedded memory applications.

The investigations of characteristics of Sb 2 Te as a base phase-change material

Abstract: Chalcogenide alloys are paid much attention in the study of nonvolatile phase-change memory (PCM). A comprehensive research is investigated on Sb2Te (ST), a base material, from properties to performances in this paper. For the characteristics of ST films, the sheet resistance is extremely stable during cooling process in resistance-temperature measurement and the thickness change of ST film is 5.7%. However, low 10-year data retention temperature (∼55 °C) and large crystal grain are the demerits for ST. In addition, the structure characteristics show stable hexagonal phase and large grain of several hundred nanometers at crystalline state after annealing. As for electrical properties, although the ST-based PCM devices are characterized by fast operation speed of ∼20 ns, only about 8 × 103 times of stable operation cycles can be obtained. After that, the endurance performance deteriorates gradually due to the growth of grains. About resistance drift, the drift coefficients are very small both in crystalline state and in amorphous state.

Multi-layer WSe2 field effect transistor with improved carrier-injection contact by using oxygen plasma treatment

Abstract: This paper investigates the effect of an oxygen (O2) plasma treatment on multi-layer tungsten diselenide (WSe2) field-effect transistor (FET) by forming tungsten trioxide (WO3) layers. Palladium (Pd), which is known to form an Ohmic contact with WSe2, is used for the source and drain (S/D) contact electrodes as a control group for metal variables. And then, Nickel (Ni), which is thought to form a Schottky contact with WSe2 experimentally, is used as an experimental group. For both cases of the control group and the experimental group, the electrical characteristics including drain current (ID), on/off ratio (ION/IOFF), subthreshold swing (SS) and field effect mobility (μeff) are analyzed according to the presence or absence of WO3. In case of adopting the WO3 contact layer between the WSe2 and the Ni for the S/D contact electrode, we observe a remarkable improvement in ID, ION/IOFF, μeff, and SS compared to the case without the WO3 contact layer. The analyzed electrical characteristics show that an efficient hole-injection contact was achieved for the multi-layer WSe2 FET by the O2 plasma treatment, which leads to the formation of an Ohmic-like contact at an electrode/WSe2 interface.

Trap states extraction of p-channel SnO thin-film transistors based on percolation and multiple trapping carrier conductions

Abstract: A new method is proposed to extract the trap states in p-channel SnO thin-film transistors (TFTs). In this method, the dominant conduction mechanisms under different temperatures have been taken into account. There are percolation and multiple trapping conduction mechanisms. Combined with the drain current-temperature ( I ds - T ) and capacitance-voltage ( C - V ) measurements, the variation of trap states concentrations with the surface potential is derived. Results show that energy-dependent density of states (DOS) is in the order of 10 19 eV/cm 3 . And the maximum of the density of states at the interface between the gate dielectric and the SnO channel is N ss = 1.77 × 10 14 cm −2 eV −1 .

GaN-based Schottky barrier ultraviolet photodetectors with graded doping on patterned sapphire substrates

Abstract: In this paper, we demonstrate high performance GaN-based Schottky-barrier ultraviolet (UV) photodetectors with graded doping prepared on patterned sapphire substrates. The fabricated devices exhibit an extremely low dark current density of ∼1.3 × 10 −8 A/cm 2 under −5 V bias, a large UV-to-visible light rejection ratio of ∼4.2 × 10 3 , and a peak external quantum efficiency of ∼50.7% at zero bias. Even in the deeper 250–360 nm range, the average external quantum efficiency still remains ∼40%. From the transient response characteristics, the average rising and falling time constants are estimated ∼115 μs and 120 μs, respectively, showing a good electrical and thermal reliability. The specific detectivities D ∗ , limited by the thermal equilibrium noise and the low-frequency 1/ f noise, are derived ∼5.5 × 10 13 cm Hz 1/2 /W (at 0 V) and ∼2.68 × 10 10 cm Hz 1/2 W −1 (at −5 V), respectively.

Reconfigurable field effect transistor for advanced CMOS: Advantages and limitations

Abstract: Reconfigurable FETs (RFETs) are optimized in planar Fully Depleted (FD) SOI. Their basics, electrostatics and performance are studied and compared with standard 28 nm FDSOI and other RFETs results in the literature. The main challenge for future broad adoption is analyzed and commented. Finally, some tips to improve the performance such as the asymmetric silicidation at source/drain are discussed.

Design and characterization of GaN p-i-n diodes for betavoltaic devices

Abstract: The performance of gallium nitride (GaN) p-i-n diodes were investigated for use as a betavoltaic device. Dark IV measurements showed a turn on-voltage of approximately 3.2 V, specific-on-resistance of 15.1 mΩ cm 2 and a reverse leakage current of −0.14 mA/cm 2 at −10 V. A clear photo-response was observed when IV curves were measured under a light source at a wavelength of 310 nm (4.0 eV). In addition, GaN p-i-n diodes were tested under an electron-beam in order to simulate common beta radiation sources ranging from that of 3 H (5.6 keV average) to 63 Ni (17 keV average). From this data, we estimated output powers of 53 nW and 750 nW with overall efficiencies of 0.96% and 4.4% for our device at incident electron energies of 5.6 keV and 17 keV corresponding to 3 H and 63 Ni beta sources respectively.

Process modules for GeSn nanoelectronics with high Sn-contents

Abstract: This paper systematically studies GeSn n-FETs, from individual process modules to a complete device. High-k gate stacks and NiGeSn metallic contacts for source and drain are characterized in independent experiments. To study both direct and indirect bandgap semiconductors, a range of 0–14.5 at.% Sn-content GeSn alloys are investigated. Special emphasis is placed on capacitance-voltage (C-V) characteristics and Schottky-barrier optimization. GeSn n-FET devices are presented including temperature dependent I-V characteristics. Finally, as an important step towards implementing GeSn in tunnel-FETs, negative differential resistance in Ge0.87Sn0.13 tunnel-diodes is demonstrated at cryogenic temperatures. The present work provides a base for further optimization of GeSn FETs and novel tunnel FET devices.

Study of line-TFET analog performance comparing with other TFET and MOSFET architectures

Abstract: In this work the Line-TFET performance is compared with MOSFET and Point-TFET devices, with different architectures (FinFET and GAA:Gate-All-Around) at both room and high temperatures. This analysis is based on the experimental basic analog parameters such as transconductance (gm), output conductance (gD) and intrinsic voltage gain (AV). Although the Line-TFETs present worse AV than the point-TFETs, when they are compared with MOSFET technology, the line-TFET shows a much better intrinsic voltage gain than both MOSFET architectures (FinFET and GAA). Besides the AV, the highest on-state current was obtained for Line-TFETs when compared with other two TFET architectures, which leads to a good compromise for analog application.

Hyperbolic metamaterials: Novel physics and applications

Abstract: Hyperbolic metamaterials were originally introduced to overcome the diffraction limit of optical imaging. Soon thereafter it was realized that hyperbolic metamaterials demonstrate a number of novel phenomena resulting from the broadband singular behavior of their density of photonic states. These novel phenomena and applications include super resolution imaging, new stealth technologies, enhanced quantum-electrodynamic effects, thermal hyperconductivity, superconductivity, and interesting gravitation theory analogues. Here we briefly review typical material systems, which exhibit hyperbolic behavior and outline important novel applications of hyperbolic metamaterials. In particular, we will describe recent imaging experiments with plasmonic metamaterials and novel VCSEL geometries, in which the Bragg mirrors may be engineered in such a way that they exhibit hyperbolic metamaterial properties in the long wavelength infrared range, so that they may be used to efficiently remove excess heat from the laser cavity. We will also discuss potential applications of three-dimensional self-assembled photonic hypercrystals, which are based on cobalt ferrofluids in external magnetic field. This system bypasses 3D nanofabrication issues, which typically limit metamaterial applications. Photonic hypercrystals combine the most interesting features of hyperbolic metamaterials and photonic crystals.

Sub-15 nm gate-all-around field effect transistors on vertical silicon nanowires

Abstract: A vertical MOS architecture implemented on Si nanowire (NW) array with a scaled Gate-All-Around (14 nm) and symmetrical diffusive S/D contacts is presented with noteworthy demonstrations in both processing (layer engineering at nanoscale), and in electrical properties (high electrostatic control, low defect level, multi-Vt platform). Furthermore, the versatility and reliability of this technology is evidenced with a CMOS inverter, providing bright perspectives for ultimate scaling.

The prospects of transition metal dichalcogenides for ultimately scaled CMOS

Abstract: MOSFET gate length scaling has been a main source of progress in digital electronics for decades. Today, researchers still spend considerable efforts on reducing the gate length and on developing ultimately scaled MOSFETs, thereby exploring both new device architectures and alternative channel materials beyond Silicon such as two-dimensional TMDs (transition metal dichalcogenide s ). On the other hand, the envisaged scaling scenario for the next 15 years has undergone a significant change recently. While the 2013 ITRS edition required a continuation of aggressive gate length scaling for at least another 15 years, the 2015 edition of the ITRS suggests a deceleration and eventually a levelling off of gate length scaling and puts more emphasis on alternative options such as pitch scaling to keep Moore’s Law alive. In the present paper, future CMOS scaling is discussed in the light of emerging two-dimensional MOSFET channel, in particular two-dimensional TMDs. To this end, the scaling scenarios of the 2013 and 2015 ITRS editions are considered and the scaling potential of TMD MOSFETs is investigated by means of quantum–mechanical device simulations. It is shown that for ultimately scaled MOSFETs as required in the 2013 ITRS, the heavy carrier effective masses of the Mo- and W-based TMDs are beneficial for the suppression of direct source-drain tunneling, while to meet the significantly relaxed scaling targets of the 2016 ITRS heavy-effective-mass channels are not needed.

Tuning the tunneling probability by mechanical stress in Schottky barrier based reconfigurable nanowire transistors

Abstract: Mechanical stress is an established and important tool of the semiconductor industry to improve the performance of modern transistors. It is well understood for the enhancement of carrier mobility but rather unexplored for the control of the tunneling probability for injection dominated research devices based on tunneling phenomena, such as tunnel FETs, resonant tunnel FETs and reconfigurable Schottky FETs. In this work, the effect of stress on the tunneling probability and overall transistor characteristics is studied by three-dimensional device simulations in the example of reconfigurable silicon nanowire Schottky barrier transistors using two independently gated Schottky junctions. To this end, four different stress sources are investigated. The effects of mechanical stress on the average effective tunneling mass and on the multi-valley band structure applying the deformation potential theory are being considered. The transfer characteristics of strained transistors in n- and p-configuration and corresponding charge carrier tunneling are analyzed with respect to the current ratio between electron and hole conduction. For the implementation of these devices into complementary circuits, the mandatory current ratio of unity can be achieved by appropriate mechanical stress either by nanowire oxidation or the application of a stressed top layer.

On recoverable behavior of PBTI in AlGaN/GaN MOS-HEMT

Abstract: This experimental study focuses on the positive bias temperature instability (PBTI) in a fully recessed-gate AlGaN/GaN MOS-HEMT. A positive stress voltage to the gate results in positive threshold voltage shift (ΔVth), which is attributed to the trapping of electrons from the GaN layer into the pre-existing oxide traps. The trapping rate exhibits a universal decreasing behavior as a function of the number of filled traps, independently of stress time, stress voltage, stress temperature, and device-to-device variability. The stress-induced ΔVth can be fully recovered by applying a small negative voltage, which causes the electron de-trapping. In the explored time window (between 1 s and thousands of s), the recovery dynamics is well described by the superimposition of two exponential functions associated with two different traps. Both trap time constants are independent of the stress voltage, decrease with temperature and increase with the recovery voltage. The activation energy of the slower trap is 0.93 eV, while the faster trap exhibits an activation energy with a large spread in the range between 0.45 eV and 0.82 eV.

An innovative large scale integration of silicon nanowire-based field effect transistors

Abstract: Since the early 2000s, silicon nanowire field effect transistors are emerging as ultrasensitive biosensors while offering label-free, portable and rapid detection. Nevertheless, their large scale production remains an ongoing challenge due to time consuming, complex and costly technology. In order to bypass these issues, we report here on the first integration of silicon nanowire networks, called nanonet, into long channel field effect transistors using standard microelectronic process. A special attention is paid to the silicidation of the contacts which involved a large number of SiNWs. The electrical characteristics of these FETs constituted by randomly oriented silicon nanowires are also studied. Compatible integration on the back-end of CMOS readout and promising electrical performances open new opportunities for sensing applications.

The signal-to-noise ratio and a hidden symmetry of Hall plates

Abstract: In a Hall plate with finite size and contacts the Hall output voltage is given by the product of sheet resistance, input current, Hall mobility, magnetic flux density, and Hall geometry factor G H . G H ∈ [ 0 , 1 ] accounts for the loss in signal due to the contacts. At weak magnetic field G H → G H 0 is a function of geometrical parameters only, which makes it the crucial point for layout optimization. We show how to express G H 0 alternatively as a function of electrical parameters only, namely of input and output resistances over sheet resistance. This allows for an analytical optimization of signal-to-noise-ratio (SNR) without getting lost in the multitude of geometrical representations of equivalent Hall plates. In the course of this investigation we notice a hidden symmetry property of G H , which we prove rigorously in the limit of small magnetic fields. The physical meaning of this symmetry in the case of Hall plates with equal input and output resistances is also explained.

Forming operation in Ge-rich Ge x Sb y Te z phase change memories

Abstract: Optimized Ge-rich Ge x Sb y Te z materials with improved crystallization temperature have been proven to guarantee code integrity after soldering thermal profile and data retention in extended temperature range for automotive application. Together with higher crystallization temperature, these materials show also peculiar characteristics of the crystalline state with respect to conventional GST (Ge 2 Sb 2 Te 5 ). In particular integrated memory cell shows a very high virgin resistance and needs an electrical activation as last operation of the fabrication process. In this paper we investigate for the first time the role of this electrical activation we named forming operation. In particular we show that the level of the maximum current flowing into the cell at the first electrical activation ( forming level ) has an impact on cell programmability. An explanation of this behavior based on physical analysis is provided suggesting that it is related to the modulation of cell thermal efficiency. Finally it is shown how forming level can be used in order to optimize cell reliability with respect to requested specifications for high temperature data retention (HTDR) and endurance.

The influence of impurity profiles on mobility of two-dimensional electron gas in AlGaAs/InGaAs/GaAs heterostructures modulation-doped by donors and acceptors

Abstract: The low-temperature mobility of two-dimensional electron gas (2DEG) limited scattering by ionized impurities, alloy disorder, acoustic and optical phonons, and interface roughness was calculated for novel pseudomorphic modulation-doped by donors and acceptors InGaAs/AlGaAs quantum well structures promising for high power microwave transistors. Due to the high 2DEG density in the quantum well intersubband transitions were taken into account. Scattering by the ionized donors from δ-layer located in AlGaAs barriers dominates, whereas scattering by the ionized acceptors occupying the most part of AlGaAs barriers is negligibly weak. The width of donor doping profile is a key parameter to control 2DEG mobility, thus, increasing of the profile width from 0.25 nm to 4 nm due to segregation and diffusion of donor atoms halves the mobility. We have proposed a few approaches for the weakening of Coulomb scattering and the increase in 2DEG mobility in the novel heterostructures. The predicted mobility enhancement due to δ-layer splitting into two δ-sublayers was verified experimentally.

Effect of oxygen content of the LaAlO 3 layer on the synaptic behavior of Pt/LaAlO 3 /Nb-doped SrTiO 3 memristors for neuromorphic applications

Abstract: We report the effect of the oxygen content of the LaAlO3 layer on the synaptic behavior in the Pt/LaAlO3/Nb-doped SrTiO3 memristor for neuromorphic applications. As the oxygen-content decreases, the current becomes larger and the spike time-dependent plasticity (STDP) becomes less sensitive to the time difference between pre- and post-synaptic spike voltage. In addition, the conduction mechanism, which was found to be a combination of thermionic and Poole-Frenkel emissions, and the effect of oxygen content are explained in association with the oxygen vacancy in the LaAlO3 layer. The trade-off between large current and efficient STDP can be controlled by the oxygen content. Furthermore, the results of extracting the synaptic strength-based model parameters indicate that the Pt/LaAlO3/Nb-doped SrTiO3 shows the efficient STDP characteristics in comparison to previously reported memristor materials.

Sensing properties of separative paper-based extended-gate ion-sensitive field-effect transistor for cost effective pH sensor applications

Abstract: In this study, we developed a cost-effective ion-sensing field-effect transistor (FET) with an extended gate (EG) fabricated on a separative paper substrate. The pH sensing characteristics of the paper EG was compared with those of other EGs fabricated on silicon, glass, or polyimide substrates. The fabricated paper-based EGFET exhibited excellent sensitivity close to the Nernst response limit as well as to that of the other substrate-based EGFETs. In addition, we found that all EGFETs, regardless of the substrate, have similar non-ideal behavior, i.e., drift phenomenon and hysteresis width. To investigate the degradation and durability of the paper EG after prolonged use, aging-effect tests were carried out in terms of the hysteresis width and sensitivity over a course of 30 days. As a result, the paper EG maintained stable pH sensing characteristics after 30 days. Therefore, we expect that paper EGFETs can provide a cost-effective sensor platform.

Novel analytical model for optimizing the pull-in voltage in a flexured MEMS switch incorporating beam perforation effect

Abstract: This paper presents a new method for the design, modelling and optimization of a uniform serpentine meander based MEMS shunt capacitive switch with perforation on upper beam. The new approach is proposed to improve the Pull-in Voltage performance in a MEMS switch. First a new analytical model of the Pull-in Voltage is proposed using the modified Mejis-Fokkema capacitance model taking care of the nonlinear electrostatic force, the fringing field effect due to beam thickness and etched holes on the beam simultaneously followed by the validation of same with the simulated results of benchmark full 3D FEM solver CoventorWare in a wide range of structural parameter variations. It shows a good agreement with the simulated results. Secondly, an optimization method is presented to determine the optimum configuration of switch for achieving minimum Pull-in voltage considering the proposed analytical mode as objective function. Some high performance Evolutionary Optimization Algorithms have been utilized to obtain the optimum dimensions with less computational cost and complexity. Upon comparing the applied algorithms between each other, the Dragonfly Algorithm is found to be most suitable in terms of minimum Pull-in voltage and higher convergence speed. Optimized values are validated against the simulated results of CoventorWare which shows a very satisfactory results with a small deviation of 0.223 V. In addition to these, the paper proposes, for the first time, a novel algorithmic approach for uniform arrangement of square holes in a given beam area of RF MEMS switch for perforation. The algorithm dynamically accommodates all the square holes within a given beam area such that the maximum space is utilized. This automated arrangement of perforation holes will further improve the computational complexity and design accuracy of the complex design of perforated MEMS switch.

Ion/Ioff ratio enhancement and scalability of gate-all-around nanowire negative-capacitance FET with ferroelectric HfO2

Abstract: We have investigated the energy efficiency and scalability of ferroelectric HfO2 (FE:HfO2)-based negative-capacitance field-effect-transistor (NCFET) with gate-all-around (GAA) nanowire (NW) channel structure. Analytic simulation is conducted to characterize NW-NCFET by varying NW diameter and/or thickness of gate insulator as device structural parameters. Due to the negative-capacitance effect and GAA NW channel structure, NW-NCFET is found to have 5× higher Ion/Ioff ratio than classical NW-MOSFET and 2× higher than double-gate (DG) NCFET, which results in wider design window for high Ion/Ioff ratio. To analyze these obtained results from the viewpoint of the device scalability, we have considered constraints regarding very limited device structural spaces to fit by the gate insulator and NW channel for aggresively scaled gate length (Lg) and/or very tight NW pitch. NW-NCFET still has design point with very thinned gate insulator and/or narrowed NW. Therefore, FE:HfO2-based NW-NCFET is applicable to the aggressively scaled technology node of sub-10 nm Lg and to the very tight NW integration of sub-30 nm NW pitch for beyond 7 nm technology.

Temperature and Electric Field Induced Metal-Insulator Transition in Atomic Layer Deposited VO2 Thin Films

Abstract: Amorphous vanadium oxide (VO 2 ) films deposited by atomic layer deposition (ALD) were crystallized with an ex situ anneal at 660–670 °C for 1–2 h under a low oxygen pressure (10 −4 to 10 −5 Torr). Under these conditions the crystalline VO 2 phase was maintained, while formation of the V 2 O 5 phase was suppressed. Electrical transition from the insulator to the metallic phase was observed in the 37–60 °C range, with an R OFF /R ON ratio of up to about 750 and ΔT C ≅ 7–10 °C. Lateral electric field applied across two-terminal device structures induced a reversible phase change, with a room temperature transition field of about 25 kV/cm in the VO 2 sample processed with the 2 h long O 2 anneal. Both the width and slope of the field induced MIT I-V hysteresis were dependent upon the VO 2 crystalline quality.

Channel scaling and field-effect mobility extraction in amorphous InZnO thin film transistors

Abstract: Amorphous oxide semiconductors (AOSs) based on indium oxides are of great interest for next generation ultra-high definition displays that require much smaller pixel driving elements. We describe the scaling behavior in amorphous InZnO thin film transistors (TFTs) with a significant decrease in the extracted field-effect mobility μ FE with channel length L (from 39.3 to 9.9 cm 2 /V·s as L is reduced from 50 to 5 μm). Transmission line model measurements reveal that channel scaling leads to a significant μ FE underestimation due to contact resistance ( R C ) at the metallization/channel interface. Therefore, we suggest a method of extracting correct μ FE when the TFT performance is significantly affected by R C . The corrected μ FE values are higher (45.4 cm 2 /V·s) and nearly independent of L . The results show the critical effect of contact resistance on μ FE measurements and suggest strategies to determine accurate μ FE when a TFT channel is scaled.

Resistive switching characteristics of solution-processed organic-inorganic blended films for flexible memory applications

Abstract: We developed a hybrid organic-inorganic resistive random access memory (ReRAM) device that uses a solution-process to overcome the disadvantages of organic and inorganic materials for flexible memory applications. The drawbacks of organic and inorganic materials are a poor electrical characteristics and a lack of flexibility, respectively. We fabricated a hybrid organic-inorganic switching layer of ReRAM by blending HfO x or AlO x solution with PMMA solution and investigated the resistive switching behaviour in Ti/PMMA/Pt, Ti/PMMA-HfO x /Pt and Ti/PMMA-AlO x /Pt structures. It is found that PMMA-HfO x or PMMA-AlO x hybrid switching layer has a larger memory window, more stable durability and retention characteristics, and a better set/reset voltage distribution than PMMA layer. Further, it is confirmed that the flexibility of the PMMA-HfO x and PMMA-AlO x blended films was almost similar to that of the organic PMMA film. Thus, the solution-processed organic-inorganic blended films are considered a promising material for a non-volatile memory device on a flexible or wearable electronic system.

Reliability improvement in GaN HEMT power device using a field plate approach

Abstract: This study investigates the effect of implementing a field plate on a GaN high-electron-mobility transistor (HEMT) to improve power device reliability. The results indicate that the field plate structure reduces the peak electrical field and interface traps in the device, resulting in higher breakdown voltage, lower leakage current, smaller current collapse, and better threshold voltage control. Furthermore, after high voltage stress, steady dynamic on-resistance and gate capacitance degradation improvement were observed for the device with the field plate. This demonstrates that GaN device reliability can be improved by using the field plate approach.