1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS

doi:10.1109/TCSII.2005.858754

Home
/
Papers
/
1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS

Journal Article•DOI•

1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS

Robert Bogdan Staszewski¹, Sudheer Vemulapalli¹, P. Vallur¹, John Wallberg¹, Poras T. Balsara² - Show less +1 more•Institutions (2)

Texas Instruments¹, University of Texas at Dallas²

13 Mar 2006-IEEE Transactions on Circuits and Systems Ii-express Briefs (IEEE)-Vol. 53, Iss: 3, pp 220-224

TL;DR: A 20-ps time-to-digital converter (TDC) realized in 90-nm digital CMOS is used as a phase/frequency detector and charge pump replacement in an all-digital phase-locked loop for a fully-compliant Global System for Mobile Communications (GSM) transceiver.

read less

Abstract: We propose and demonstrate a 20-ps time-to-digital converter (TDC) realized in 90-nm digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an all-digital phase-locked loop for a fully-compliant Global System for Mobile Communications (GSM) transceiver. The TDC core is based on a pseudodifferential digital architecture that makes it insensitive to nMOS and pMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. It additionally serves as a CMOS process strength estimator for analog circuits in this large system-on-chip. Measured integral nonlinearity is 0.7 least significant bits. The TDC consumes 5.3 mA raw and 1.3 mA with power management from a 1.3-V supply.

...read moreread less

Citations

PDF

Open Access

More filters

Journal Article•DOI•

A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue

[...]

Minjae Lee¹, Asad A. Abidi¹•Institutions (1)

University of California, Los Angeles¹

31 Mar 2008-IEEE Journal of Solid-state Circuits

TL;DR: A new coarse-fine TDC architecture is proposed by using an array of time amplifiers and two identical fine TDCs that compensate for the variation of the TA gain during the conversion process, which will improve the linearity further.

...read moreread less

Abstract: This paper presents the design of a coarse-fine time-to-digital converter (TDC) that amplifies a time residue to improve time resolution, similar to a coarse-fine analog-to-digital converter (ADC). A new digital circuit has been developed to amplify the time residue with a higher gain (>16) and larger range (>80 ps) than existing solutions do. However, adapting the conventional coarse-fine architecture from ADCs is not an appropriate solution for TDCs: input time cannot be stored, and the gain of a time amplifier (TA) cannot be controlled precisely. This paper proposes a new coarse-fine TDC architecture by using an array of time amplifiers and two identical fine TDCs that compensate for the variation of the TA gain during the conversion process. The measured DNL and INL are plusmn0.8 LSB and plusmn3 LSB, respectively, with a value of 1.25 ps per 1 LSB, while the standard deviation of output code for constant inputs remains below 1 LSB across the TDC range. Although the nonlinearity is larger than 1 LSB, using an INL lookup table or better matched delays in the coarse TDC delay chain will improve the linearity further.

...read moreread less

465 citations

Cites background or methods from "1.3 V 20 ps time-to-digital convert..."

...A delay-locked loop (DLL) can be used to control the delay in the CTDC chain [1], [4], [9], [10], [12], or period estimation in the digital PLL [ 3 ] makes it possible to compensate the variation while it is operating....
[...]
...However, conventional flip-flops, such as the sense-amplifier-based flip-flop in [ 3 ], create mismatch in the data and clock propagation path, which results in a large time offset....
[...]
...The delay chain of buffers [1], [ 3 ] and the Vernier delay line [4] are well-known methods to realize a TDC....
[...]
...It has been reported that using an inverter chain introduces uneven delay characteristics due to the rise and fall time mismatch of the inverter and the asymmetric flip-flop characteristics for the low-to-high and high-to-low input transition [ 3 ]....
[...]

Journal Article•DOI•

A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping

[...]

M.Z. Straayer, Michael H. Perrott

24 Mar 2009-IEEE Journal of Solid-state Circuits

TL;DR: An 11-bit, 50-MS/s time-to-digital converter (TDC) using a multipath gated ring oscillator with 6 ps of effective delay per stage demonstrates 1st-order noise shaping.

...read moreread less

Abstract: An 11-bit, 50-MS/s time-to-digital converter (TDC) using a multipath gated ring oscillator with 6 ps of effective delay per stage demonstrates 1st-order noise shaping. At frequencies below 1 MHz, the TDC error integrates to 80 fs (rms) for a dynamic range of 95 dB with no calibration required. The 157 times 258 mum TDC is realized in 0.13 mum CMOS and, depending on the time difference between input edges, consumes 2.2 to 21 mA from a 1.5 V supply.

...read moreread less

340 citations

Cites background from "1.3 V 20 ps time-to-digital convert..."

...Digital Object Identifier 10.1109/JSSC.2009.2014709 an active research topic in the mixed-signal circuit community [5]–[10]....
[...]

Journal Article•DOI•

A Low-Noise Wide-BW 3.6-GHz Digital $\Delta\Sigma$ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation

[...]

Chun-Ming Hsu¹, M.Z. Straayer, Michael H. Perrott•Institutions (1)

IBM¹

12 Dec 2008-IEEE Journal of Solid-state Circuits

TL;DR: A 3.6-GHz digital fractional-N frequency synthesizer achieving low noise and 500-kHz bandwidth is presented, which uses a gated-ring-oscillator time-to-digital converter to achieve integrated phase noise of less than 300 fs.

...read moreread less

Abstract: A 3.6-GHz digital fractional-N frequency synthesizer achieving low noise and 500-kHz bandwidth is presented. This architecture uses a gated-ring-oscillator time-to-digital converter (TDC) with 6-ps raw resolution and first-order shaping of its quantization noise along with digital quantization noise cancellation to achieve integrated phase noise of less than 300 fs (1 kHz to 40 MHz). The synthesizer includes two 10-bit 50-MHz passive digital-to-analog converters for digital control of the oscillator and an asynchronous frequency divider that avoids divide-value delay variation at its output. Implemented in a 0.13-mum CMOS process, the prototype occupies 0.95-mm2 active area and dissipates 39 mW for the core parts with another 8 mW for the oscillator output buffer. Measured phase noise at 3.67 GHz carrier frequency is -108 and -150 dBc/Hz at 400 kHz and 20 MHz offset, respectively.

...read moreread less

325 citations

Cites methods or result from "1.3 V 20 ps time-to-digital convert..."

...For a classical TDC structure [5], the TDC resolution corresponds to an inverter delay, and the goal of 6-ps resolution ends...
[...]
...By doing so, the raw resolution corresponds to an inverter delay, which is similar to the case for the commonly used TDC described in [5]....
[...]

Proceedings Article•DOI•

A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation

[...]

Chun-Ming Hsu¹, M.Z. Straayer¹, Michael H. Perrott¹•Institutions (1)

Massachusetts Institute of Technology¹

01 Feb 2008

TL;DR: A digital fractional-N frequency synthesizer is presented that leverages a noise-shaping time-to-digital converter (TDC) and a simple quantization noise cancellation technique to achieve low phase noise with a wide PLL bandwidth of 500kHz.

...read moreread less

Abstract: A digital fractional-N frequency synthesizer is presented that leverages a noise-shaping time-to-digital converter (TDC) and a simple quantization noise cancellation technique to achieve low phase noise with a wide PLL bandwidth of 500kHz. In contrast to previous cancellation techniques, this structure requires no analog components and is straightforward to implement with standard-cell digital logic.

...read moreread less

233 citations

Cites methods or result from "1.3 V 20 ps time-to-digital convert..."

...For a classical TDC structure [5], the TDC resolution corresponds to an inverter delay, and the goal of 6-ps resolution ends...
[...]
...By doing so, the raw resolution corresponds to an inverter delay, which is similar to the case for the commonly used TDC described in [5]....
[...]

Journal Article•DOI•

CMOS Imager With 1024 SPADs and TDCs for Single-Photon Timing and 3-D Time-of-Flight

[...]

Federica Villa¹, Rudi Lussana¹, Danilo Bronzi¹, Simone Tisa, Alberto Tosi¹, Franco Zappa¹, Alberto Dalla Mora¹, Davide Contini¹, Daniel Durini², Sascha Weyers³, Werner Brockherde³ - Show less +7 more•Institutions (3)

Polytechnic University of Milan¹, Forschungszentrum Jülich², Fraunhofer Society³

23 Jul 2014-IEEE Journal of Selected Topics in Quantum Electronics

TL;DR: In this article, the authors present a CMOS imager consisting of 32×32 smart pixels, each one able to detect single photons in the 300-900 nm wavelength range and to perform both photon-counting and photon-timing operations on very fast optical events with faint intensities.

...read moreread less

Abstract: We present a CMOS imager consisting of 32×32 smart pixels, each one able to detect single photons in the 300-900 nm wavelength range and to perform both photon-counting and photon-timing operations on very fast optical events with faint intensities. In photon-counting mode, the imager provides photon-number (i.e, intensity) resolved movies of the scene under observation, up to 100 000 frames/s. In photon-timing, the imager provides photon arrival times with 312 ps resolution. The result are videos with either time-resolved (e.g., fluorescence) maps of a sample, or 3-D depth-resolved maps of a target scene. The imager is fabricated in a cost-effective 0.35-μm CMOS technology, automotive certified. Each pixel consists of a single-photon avalanche diode with 30 μm photoactive diameter, coupled to an in-pixel 10-bit time-to-digital converter with 320-ns full-scale range, an INL of 10% LSB and a DNL of 2% LSB. The chip operates in global shutter mode, with full frame times down to 10 μs and just 1-ns conversion time. The reconfigurable imager design enables a broad set of applications, like time-resolved spectroscopy, fluorescence lifetime imaging, diffusive optical tomography, molecular imaging, time-of-flight 3-D ranging and atmospheric layer sensing through LIDAR.

...read moreread less

218 citations

Cites methods from "1.3 V 20 ps time-to-digital convert..."

...ranges could be achieved through interpolation methods based for instance on Pulse-Shrinking delay line [23], Tapped delay line [24], or standard and cyclic Vernier delay line [25] elements....
[...]

1
2
3
4
…
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74

Collapse

References

PDF

Open Access

More filters

Journal Article•DOI•

A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line

[...]

Piotr Dudek¹, S. Szczepanski, J.V. Hatfield•Institutions (1)

University of Manchester¹

01 Feb 2000-IEEE Journal of Solid-state Circuits

TL;DR: Test results show that even higher resolutions can be achieved using the VDL method, and resolutions down to 5 ps are demonstrated to be obtainable.

...read moreread less

Abstract: This paper describes a CMOS time-to-digital converter (TDC) integrated circuit utilizing tapped delay lines. A technique that allows the achievement of high resolution with low dead-time is presented, The technique is based on a Vernier delay line (VDL) used in conjunction with an asynchronous read-out circuitry. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. A test circuit fabricated in a standard 0.7-/spl mu/m digital CMOS process is presented. The TDC contains 128 delay stages and achieves 30-ps resolution, stabilized by the DLL, with the accuracy exceeding /spl plusmn/1 LSB. Test results show that even higher resolutions can be achieved using the VDL method, and resolutions down to 5 ps are demonstrated to be obtainable.

...read moreread less

724 citations

"1.3 V 20 ps time-to-digital convert..." refers methods in this paper

...T IME-TO-DIGITAL converters (TDCs) are being widely used for time interval measurements in space science [1], [2], high-energy physics [3]–[5], laser range finders [6] and test instrumentation [7]....
[...]
...Other TDC architectures are based on a Vernier line [3] and pulse-shrinking techniques [1], [6]....
[...]

Journal Article•DOI•

Improved sense-amplifier-based flip-flop: design and measurements

[...]

Borivoje Nikolic¹, Vojin G. Oklobdzija², Vladimir Stojanovic³, Wenyan Jia⁴, James Kar Shing Chiu⁴, M. Ming-Tak Leung⁴ - Show less +2 more•Institutions (4)

University of California, Berkeley¹, University of California, Davis², Stanford University³, Texas Instruments⁴

01 Jun 2000-IEEE Journal of Solid-state Circuits

TL;DR: The design and experimental evaluation of a new sense-amplifier-based flip-flop (SAFF) is presented and it is found that the main speed bottleneck of existing SAFF's is the cross-coupled set-reset (SR) latch in the output stage.

...read moreread less

Abstract: Design and experimental evaluation of a new sense-amplifier-based flip-flop (SAFF) is presented. It was found that the main speed bottleneck of existing SAFF's is the cross-coupled set-reset (SR) latch in the output stage. The new flip-flop uses a new output stage latch topology that significantly reduces delay and improves driving capability. The performance of this flip-flop is verified by measurements on a test chip implemented in 0.18 /spl mu/m effective channel length CMOS. Demonstrated speed places it among the fastest flip-flops used in the state-of-the-art processors. Measurement techniques employed in this work as well as the measurement set-up are discussed in this paper.

...read moreread less

436 citations

"1.3 V 20 ps time-to-digital convert..." refers methods in this paper

...The delayed-clock replica vector is sampled by FREF using an array of 48 sense-amplifier-based flip-flops that are adapted from [13]....
[...]

Proceedings Article•DOI•

All-digital PLL and GSM/EDGE transmitter in 90nm CMOS

[...]

Robert Bogdan Staszewski¹, John Wallberg¹, Sameh S. Rezeq¹, Chih-Ming Hung¹, Oren Eliezer¹, Sudheer Vemulapalli¹, C. Fernando¹, Kenneth J. Maggio¹, Robert B. Staszewski¹, N. Barton¹, Meng-Chang Lee¹, P. Cruise¹, Manouchehr Entezari¹, Khurram Muhammad¹, Dirk Leipold¹ - Show less +11 more•Institutions (1)

Texas Instruments¹

29 Aug 2005

TL;DR: A 1.2V 42mA all-digital PLL and polar transmitter for a single-chip GSM/EDGE transceiver is implemented in 90nm CMOS and achieves -165dBc/Hz phase noise at 20MHz offset, with 10 /spl mu/s settling time.

...read moreread less

Abstract: A 1.2V 42mA all-digital PLL and polar transmitter for a single-chip GSM/EDGE transceiver is implemented in 90nm CMOS. It transmits GMSK with 0.5/spl deg/ rms phase error and achieves -165dBc/Hz phase noise at 20MHz offset, with 10 /spl mu/s settling time. A digitally controlled 6dBm class-E PA modulates the amplitude and meets the EDGE spectral mask with 3.5% EVM.

...read moreread less

176 citations

"1.3 V 20 ps time-to-digital convert..." refers methods in this paper

...A very recent [12] culminates in a TDC-based frequency synthesizer for a fully-compliant Global System for Mobile Communications...
[...]

Journal Article•DOI•

A high-resolution time interpolator based on a delay locked loop and an RC delay line

[...]

M. Mota¹, J. Christiansen¹•Institutions (1)

CERN¹

01 Oct 1999-IEEE Journal of Solid-state Circuits

TL;DR: An architecture for a time interpolation circuit with an rms error of /spl sim/25 ps has been developed in a 0.7-/spl mu/m CMOS technology based on a delay locked loop driven by a 160-MHz reference clock and a passive RC delay line controlled by an autocalibration circuit.

...read moreread less

Abstract: An architecture for a time interpolation circuit with an rms error of /spl sim/25 ps has been developed in a 0.7-/spl mu/m CMOS technology. It is based on a delay locked loop (DLL) driven by a 160-MHz reference clock and a passive RC delay line controlled by an autocalibration circuit. Start-up calibration of the RC delay line is performed using code density tests (CDT). The very small temperature/voltage dependence of R and C parameters and the self calibrating DLL results in a low-power, high-resolution time interpolation circuit in a standard digital CMOS technology.

...read moreread less

154 citations

"1.3 V 20 ps time-to-digital convert..." refers methods in this paper

...The selection method is similar to [5] but only one counter is used....
[...]
...T IME-TO-DIGITAL converters (TDCs) are being widely used for time interval measurements in space science [1], [2], high-energy physics [3]–[5], laser range finders [6] and test instrumentation [7]....
[...]

Journal Article•DOI•

A low-power CMOS time-to-digital converter

[...]

E. Raisanen-Ruotsalainen¹, Timo Rahkonen¹, Juha Kostamovaara¹•Institutions (1)

University of Oulu¹

01 Sep 1995-IEEE Journal of Solid-state Circuits

TL;DR: In this paper, a time-to-digital converter (TDC) with 780 ps lsb and 10-spl mu/s input range has been integrated in a 1.2-/spl µ/m CMOS technology.

...read moreread less

Abstract: A time-to-digital converter, TDC, with 780 ps lsb and 10-/spl mu/s input range has been integrated in a 1.2-/spl mu/m CMOS technology. The circuit is based on the interpolation time interval measurement principle and contains an amplitude regulated crystal oscillator, a counter, two pulse-shrinking delay lines, and a delay-locked loop for stabilization of the delay. The TDC is designed for a portable, low-power laser range-finding device. The supply voltage is 5/spl plusmn/0.5 V, and the operating temperature range is -40 to +60/spl deg/C. Single-shot accuracy is 3 ns and accuracy after averaging is /spl plusmn/120 ps with input time intervals 5-500 ns. In the total input range of 10 /spl mu/s, the final accuracy after averaging is /spl plusmn/200 ps. Current consumption is 3 mA, and the chip size is 2.9 mm/spl times/2.5 mm. >

...read moreread less

123 citations

"1.3 V 20 ps time-to-digital convert..." refers methods in this paper

...T IME-TO-DIGITAL converters (TDCs) are being widely used for time interval measurements in space science [1], [2], high-energy physics [3]–[5], laser range finders [6] and test instrumentation [7]....
[...]
...Other TDC architectures are based on a Vernier line [3] and pulse-shrinking techniques [1], [6]....
[...]