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Title 1-b Observation for Direct-Learning-Based Digital Predistortion of RF Power Amplifiers
Authors(s) Wang, Haoyu; Li, Gang; Zhou, Chongbin; Zhu, Anding; et al.
Publication date 2017-01-23
Publication information IEEE Transactions on Microwave Theory and Techniques, PP (99): 1-11
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1
1-Bit Observation for Direct Learning Based
Digital Predistortion of RF Power Amplifiers
Haoyu Wang, Gang Li, Chongbin Zhou, Wei Tao, Falin Liu, and Anding Zhu, Senior Member, IEEE
Abstract—In this paper, we propose a low-cost data acquisition
approach for model extraction of digital predistortion (DPD) of
RF power amplifiers. The proposed approach utilizes only 1-bit
resolution analog-to-digital converters (ADCs) in the observation
path to digitize the error signal between the input and output
signals. The DPD coefficients are then estimated based on the
direct learning architecture using the measured signs of the
error signal. The proposed solution is proved to be feasible in
theory and the experimental results show that the proposed
algorithm achieves equivalent performance as that using the
conventional method. Replacing high resolution ADCs with 1-
bit comparators in the feedback path can dramatically reduce
the power consumption and cost of the DPD system. The 1-bit
solution also makes DPD become practically implementable in
future broadband systems since it is relatively straightforward
to achieve an ultra-high sampling speed in data conversion by
using only simple comparators.
Index Terms—Analog-to-digital converter (ADC), digital pre-
distortion (DPD), error signal, linearization, low resolution,
power amplifier (PA), wideband.
I. INTRODUCTION
I
N the past twenty years or so, digital predistortion (DPD)
has become one of the most popular linearization tech-
niques for radio frequency (RF) power amplifiers (PAs) in
wireless communication systems, especially in cellular base
stations [1], [2]. Although it already seems to be a well-
established technique at current stage, DPD is still facing
new challenges since the development of the next generation
communication system never stops [2], [3]. For instance, most
current DPD solutions are employed in middle to high power
base stations where power consumption and cost of DPD units
are negligible [2]. In future networks, small-cell base stations
will be deployed, where the output power of the PA becomes
much lower and thus the power consumption and cost of the
digital components become an issue. There are many efforts
having been made to address this issue. One idea is to employ
new algorithms to simplify the DPD model. For example,
compressed sensing (CS) has recently been introduced to DPD
to reduce the model complexity [4]–[6]. It also has been
shown that some of the distortion compensation, that is usually
done at the transmitter side, can be moved to the receiver
This work was supported in part by the National Natural Science Foundation
of China under Grant Number 61471333 and by the Science Foundation
Ireland under Grant Numbers 13/RC/2077 and 12/IA/1267.
H. Wang, G. Li, C. Zhou, W. Tao and F. Liu are with the Department of
Electronic Engineering and Information Science, University of Science and
Technology of China, and also with the Key Laboratory of Electromagnetic S-
pace Information, Chinese Academy of Sciences, Hefei, Anhui, China (e-mail:
{wamhoyle; lgml; zhouzcb; jxtaowei}@mail.ustc.edu.cn; liufl@ustc.edu.cn).
A. Zhu is with the School of Electrical and Electronic Engineering,
University College Dublin, Dublin 4, Ireland (e-mail: anding.zhu@ucd.ie).
side, to reduce the complexity and power consumption of the
transmitters in small cells [7], [8].
One of the main concerns in DPD implementation is the
bandwidth requirement of the feedback path that is used to
capture the output signal from the PA for the purpose of
model extraction. With carrier aggregation (CA), the signal
bandwidth in long-term evolution-advanced (LTE-A) is up to
100 MHz already and it will be increased to 160 MHz or wider
soon [3]. For the coming 5th generation (5G) systems, the
signal bandwidth will be even wider. In DPD, the bandwidth
of the feedback path usually requires five times of the signal
bandwidth which means that mutli-giga samples per second
(GSPS) analog-to-digital converters (ADCs) are required. The
existing and forthcoming data converter technologies, however,
could hardly meet this requirement.
Some solutions have been proposed to reduce the sig-
nal bandwidth requirement. The band-limited method was
proposed in [9] but it requires an extra bandpass filter in
the RF transmit chain that is difficult and costly to design.
The analog aliased sampling method in [10] can reduce the
sampling rate but it needs additional analog aliasing operation.
The spectral extrapolation based algorithm was reported in
[11] and in [12] a forward model was first carried out and
then DPD coefficients can be estimated. In [13] a two-stage
DPD, i.e., a static nonlinear box cascaded with a dynamic
weak nonlinear box, was proposed to decrease the feedback
bandwidth. The method proposed in [14] was designed just for
concurrent dual-band signals. All of the methods mentioned
above require the acquisition bandwidth not narrower than
the signal bandwidth. Contrarily, [15] proposed an algorithm
based on random demodulation, with which an ultra-narrow
feedback bandwidth is enough for wideband DPD, but it
requires an extra random sequence generator in the analog
domain which is hard to implement due to the cost and time-
alignment issue.
Besides the sampling rate, the other issue relating to ADC
is the resolution. Before training the DPD model, the output
signal of the PA is digitized. The number of quantization bits
depends on the actual system requirement. Usually in a real
system, a 14-bit ADC is needed to give a minimum noise floor
of -70 dBc [16]. Designing a 14-bit ADC with multi-GSPS is
very challenging and costly [17]. It is therefore desirable that
the required resolution can be reduced; however, this is not a
straightforward task, since reducing the resolution of ADC is
equivalent to increasing the noise floor of the feedback signal,
which is critical to the accuracy of DPD modeling. Y. Liu et
al. proposed a method in [18] to reduce the ADC dynamic
range, but a minimum 8-bit ADC is required for achieving
2
comparable linearization performance with the conventional
DPD. A 1-bit estimator was proposed to quantize the phase
of the original input signal in [19] to reduce the complexity
of model identification while the resolution requirement for
ADCs remains the same.
In this paper, a novel direct learning architecture (DLA)
based 1-bit quantization method is proposed. The proposed
method utilizes only 1-bit resolution comparators to measure
the error signal that is then used for DPD coefficients training.
The proposed approach dramatically reduces the cost of the
feedback chain. Moreover, both theoretical derivation and
experimental tests show that the proposed method can be
extended to the systems transmitting very wideband signals.
This paper is organized as follows. Section II introduces
the proposed 1-bit observation method after reviewing the
conventional direct learning architecture. In Section III, the
time alignment, power alignment, optimization of convergence
speed and the overall system complexity are discussed. The
experimental results are given in Section IV, followed by a
conclusion in Section V.
II. THEORETICAL DERIVATION
The principle of DPD is that a digital block, called predis-
torter, is inserted into the transmitter chain to preprocess the
input signal before it enters the RF PA. If the two nonlinear
systems, i.e., the predistorter and the PA, exactly invert each
other, a highly linear system can be achieved. In order to
extract the coefficients of the predistorter, a small fraction
of the transmit signal is transferred back to baseband via
a feedback loop. Two architectures are generally employed
for model extraction: direct learning and indirect learning
architecture (IDLA). The difference between DLA and IDLA
has been investigated in [20]. The IDLA estimates the post-
inverse of the PA first and then copies the coefficients of the
post-inverse estimator to the pre-inverse one. The IDLA can
be run in an open-loop fashion. While the DLA is usually
used in closed-loop systems and it compares the PA output
with the original input directly. In low resolution systems, the
performance of IDLA is limited, while DLA is able to identify
the changes between input and output signals effectively,
especially in the 1-bit method we will propose in Section II.B.
As a result, the DLA is used for DPD modeling in this paper.
A. Conventional Direct Learning Architecture
The simplified conventional DLA block diagram is shown
in Fig. 1 [21], [22], where the bold lower-case vectors x and y
represents the input and output sequences, respectively. More
specifically, x and y are expressed as
x = [x(n − K + 1), x(n − K + 2), . . . , x(n)]
T
∈ C
K×1
,
y = [y(n −K + 1), y(n − K + 2), . . . , y(n)]
T
∈ C
K×1
,
(1)
where K is the length of the sequences used for training,
x(n) and y(n), n ∈ Z are baseband input and output signals,
respectively, and ()
T
denotes the matrix transpose. The output
of digital predistorter is denoted by z(n), and its corresponding
vector form is z. Various behavioral models can be used to
DPD PA
Model
coefficients
extraction
x
z
y
Fig. 1. Simplified DPD block diagram based on direct learning architecture.
describe the input-output relationship of the DPD [1]–[3]. For
instance, the baseband equivalent expression of Volterra model
is given by
z(n) =
P
p=1
p:odd
M
m
1
=0
···
M
m
p
=0
h
p
(m
1
, . . . , m
p
)
×
(p+1)/2
l=1
x(n − m
l
)
p
l=1+(p+1)/2
x
∗
(n − m
l
),
(2)
where h
p
is the p-th order Volterra kernel, P and M are the
nonlinear order and memory depth, respectively, and (2) can
be rewritten in a matrix form as
z = Xh. (3)
In (3), each row of X ∈ C
K×L
consists of all of the product
terms appearing in (2), and h ∈ C
L×1
is the coefficient vector
with the length of L. Let g() be the transfer function of PA,
then the output of PA can be expressed as
y = g(z) = g(Xh). (4)
The cost function of the DLA-based DPD system is the
l
2
norm of the difference between the output and input of
the system, i.e., ∥y − x∥
2
2
. Newtons method is one of the
most popular candidates that solve this kind of nonlinear
problem. To do so, the Jacobian and Hessian matrices, i.e.,
first-order and second-order derivatives of the cost function,
are calculated first. Then the DPD coefficients can be updated
in an iterative procedure [11], [21], [22]:
h
k+1
= h
k
− µ
X
H
X
−1
X
H
(y − x), (5)
where ()
H
represents the Hermitian transpose, and the damp-
ing factor µ 6 1.
To achieve a relatively good performance using (5), one
needs high resolution of the feedback signal, e.g., 14-bit
ADC to digitize the output of PA, which is one of the main
bottlenecks for DPD applications in the next generation com-
munication systems. In the next subsection, we will discuss
the detail of the proposed novel 1-bit observation algorithm,
which exhibits comparative performance with the conventional
method.
B. Proposed 1-Bit Observation for Direct Learning Based
Digital Predistortion
In a DLA-based DPD system, the difference between the
output and input signals, y(n) − x(n), should be properly
3
measured sample by sample, as demonstrated in (5). Both
x(n) and y(n) are baseband complex values, consisting of
the in-phase and quadrature (I/Q) signals. They have the form
of
x(n) = x
I
(n) + j · x
Q
(n),
y(n) = y
I
(n) + j · y
Q
(n),
(6)
where x
I
(n), x
Q
(n), y
I
(n) and y
Q
(n) are all real values.
An arbitrary real number can be written in the way that its
sign multiplies its magnitude, i.e., a = sign(a) · |a|, a ∈ R.
If the magnitude information |a| is already known or can be
estimated in an easy way, sign(a) is the only thing that needs
to be measured to calculate the number a.
By defining ∆
I
(n) = y
I
(n)−x
I
(n) and ∆
Q
(n) = y
Q
(n)−
x
Q
(n) as the error samples for the real and imaginary parts,
respectively, the difference between the output and input can
be expressed as
y(n) − x(n) = (y
I
(n) − x
I
(n)) + j · (y
Q
(n) − x
Q
(n))
= sign (∆
I
(n)) |∆
I
(n)|
+ j · sign (∆
Q
(n)) |∆
Q
(n)|.
(7)
Because PA is a nonlinear device, without linearization, sig-
nificant distortion can be introduced into the transmit signal,
especially if the PA is run into deep compression. In a real
application, however, e.g., LTE, the signal has non-constant
envelope and the amplitude of the signal follows a Gaussian-
like distribution. Only a small percentage of the signal with
high amplitudes is affected severely by the deep compression.
The magnitudes of the most error samples are relatively small,
compared to the original input. Furthermore, although |∆
I
(n)|
and |∆
Q
(n)| could hardly be strictly equal, they have the
same statistical properties and during DPD training, the errors
decrease with the number of iterations and they both approach
zero when the training converges. In this work, during the
model training process, we assume that the magnitude of
the error sample I/Q can be approximately made equal to
an updating constant, namely, |∆
I
(n)| ≈ |∆
Q
(n)| ≈ ˆc(n).
Equation (7) then becomes
y(n) − x(n) ≈ ˆc(n) (sign (∆
I
(n)) + j · sign (∆
Q
(n)))
= ˆc(n)sign (∆(n)) ,
(8)
where ∆(n) = ∆
I
(n) + j ·∆
Q
(n) and sign(∆(n)) calculates
the signs of real and imaginary parts of ∆(n) separately. The
vector form for (8) is given by
y − x = [∆(n − K + 1), ∆(n − K + 2), . . . , ∆(n)]
T
≈
ˆc(n − K + 1)sign (∆(n − K + 1))
.
.
.
ˆc(n)sign (∆(n))
≈ ˆc[sign (∆(n − K + 1)) , . . . , sign (∆(n))]
T
, ˆc · ∆
s
,
(9)
where ∆
s
is defined as a column vector that consists of the
signs of each I/Q sample. By substituting (9) into (5), it yields
h
k+1
= h
k
− ˆc
k
X
H
X
−1
X
H
∆
s
. (10)
I
Q
conventional
proposed
error
samples
proposed
1
1
-1
-1
( appropriate )
ˆ
k
c
ˆ
1
k
c
=
( )
Fig. 2. Demonstration of the relationship between conventional DPD and the
proposed 1-bit DPD.
As it can be seen, the data matrix X is already known, and
ˆc
k
is treated as the step size for the k-th iteration. Note that
the damping factor µ in (5) is combined into ˆc
k
to simplify
the expression and this has no impact on the final result. Only
the sign information of the error signal is thus needed for
conducting the calculation in (10). This enables using 1-bit
ADCs to digitize the error signal.
The difference between the proposed algorithm in (10) and
the conventional one in (5) is demonstrated in Fig. 2. The
grey dots are the error samples, and the circle in black line
denotes the objective of the conventional method with radius
equaling the root mean square (RMS) of magnitudes of the
error samples, while the two squares represent the targets of
the proposed method with different step sizes. In the proposed
algorithm, the error samples are approximately averaged to
the vertexes of the square, e.g., the error samples in the first
quadrat are moved to the upper-right vertex of the square.
Equation (10) is similar to that used in the simultaneous
perturbation method [23], [24], where a Bernoulli process
is carried out to estimate the gradient. How to choose an
appropriate step size ˆc
k
is critical. If it is properly chosen,
(10) achieves comparative performance as (5). This issue will
be discussed in detail in Section III.
III. SYSTEM IMPLEMENTATION
A. System Description
The block diagram of the proposed 1-bit observation DPD
system is illustrated in Fig. 3. The main difference from
the conventional DPD is that, in the feedback path, after
demodulation, the analog I and Q signal is sent to a comparator
to compare with the original input, respectively, to obtain the
sign of the error signal, instead of being fully digitized. In this
configuration, an additional digital to analog conversion path,
path 2 as highlighted in Fig. 3, is added to convert the original
digital I/Q to the analog domain to make the comparison. The
4
DPD QMod PA
LO
QDmod
Attenuator
I
Q
I
Q
Comparators
(1-bit ADCs)
I: Time delay
estimate
II:DPD
training
I: Time-delay estimation mode
II: DPD training mode
delay
delay
( )
I
x t
( )
Q
x t
( )
I
y t
( )
Q
y t
I
x
Q
x
( )
I
sign
Δ
GND
DAC
DAC
Digital Domain
Analog Domain
( )
Q
sign
Δ
+
-
+
-
path 2
path 1
SW-I-2
SW-II
SW-II
SW-I-1 SW-I-2
SW-I-1
SW-II
SW-II
Fig. 3. Proposed 1-bit observation DPD system.
comparators here are equivalent to the conventional ADCs
working with only 1-bit. The signs of the error signal are then
sent to the DPD training block for model extraction.
Before model extraction, time delay between the input and
output samples must be properly calibrated. In the conven-
tional system, time alignment is conducted in the digital
domain by comparing the input and output data samples.
In the proposed system, because only 1-bit comparators are
used, the high resolution output samples are not available. A
special time alignment methodology must be developed, which
will be discussed in the following subsection. To facilitate
time alignment, the sign of the output signal can be obtained
by using the existing comparators with the reference level
switched to ground, shown in Fig. 3.
Another issue is power alignment. In the conventional sys-
tem, power alignment is also done in the digital domain in both
conventional DLA-based and IDLA-based DPDs [25], [26]. In
the proposed system, power alignment must be carried out in
the analog domain, because only the input and output signal
levels are aligned properly, the sign of the error signal then
be obtained correctly. The attenuation level of the attenuator
thus must be properly chosen to ensure the powers between
input and output signals are aligned before they enter the
comparators. In real systems, some power control modules,
e.g., variable gain amplifiers (VGAs) [27], can be applied to
facilitate the implementation.
B. Time-Alignment Algorithm
Calculating cross-correlation between the input and output
signals in the time domain [28] for time alignment is a com-
mon approach in the conventional DPD training algorithms.
This is, however, not practical in the proposed system, since
only the signs of the output signal can be obtained. Directly
calculating the cross-correlation between the signs of the input
and output in the time domain will cause large errors. In this
paper, instead, we suggest to use the frequency domain based
algorithm to estimate the time delay [29], [30].
Fourier transform (FT) states that a delay in the time domain
is equivalent to a phase rotation in the frequency domain.
The time delay can thus be calculated from the measured
phase rotation in the frequency domain. For a given set of
time domain data samples, after discrete Fourier transform
(DFT), the phase-frequency relation is a simple linear function
expressed as
φ = s · f + b, (11)
where φ and f are phase rotation and frequency, respectively,
s is the slope which is directly proportional to the time delay,
b is a constant related to phase shift in the time domain. s and
b can be estimated by using the least squares (LS) algorithm
with the frequency domain data samples. Once the slope s is
obtained, the time delay is calculated as
t
delay
= −
N ˆs
2π
, (12)
where N is the total number of samples used for DFT
calculation, and ˆs is the estimated slope for s in (11).
The reason why the time domain cross-correlation does not
work in this case is because the signal amplitudes are only
at two levels. If we transform it into the frequency domain,
however, the signal power in in-band is still much higher than
the noise floor, despite of high quantization noise. This is
illustrated in Fig. 4 where the spectra of a LTE signal with
different time domain resolutions are given. To simplify the
illustration, only quantization noise is considered here. From
the figure, we can see that the noise floor increases while the
number of bits reduces. Despite the high noise floor with 1-
bit sampling, the signal power in in-band is higher than the
noise about 6 dB. If we use these in-band values to form the
equation in (11), we should be able to find the slope s and
thus calculate the time delay between the input and output