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Journal Article•DOI•

1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS

TL;DR: In this article, a multithreshold-voltage CMOS (MTCMOS) based low-power digital circuit with 0.1-V power supply high-speed low power digital circuit technology was proposed, which has brought about logic gate characteristics of a 1.7ns propagation delay time and 0.3/spl mu/W/MHz/gate power dissipation with a standard load.
Abstract: 1-V power supply high-speed low-power digital circuit technology with 0.5-/spl mu/m multithreshold-voltage CMOS (MTCMOS) is proposed. This technology features both low-threshold voltage and high-threshold voltage MOSFET's in a single LSI. The low-threshold voltage MOSFET's enhance speed performance at a low supply voltage of 1 V or less, while the high-threshold voltage MOSFET's suppress the stand-by leakage current during the sleep period. This technology has brought about logic gate characteristics of a 1.7-ns propagation delay time and 0.3-/spl mu/W/MHz/gate power dissipation with a standard load. In addition, an MTCMOS standard cell library has been developed so that conventional CAD tools can be used to lay out low-voltage LSI's. To demonstrate MTCMOS's effectiveness, a PLL LSI based on standard cells was designed as a carrying vehicle. 18-MHz operation at 1 V was achieved using a 0.5-/spl mu/m CMOS process. >
Citations
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Journal Article•DOI•
29 Apr 2003
TL;DR: Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.
Abstract: High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.

2,281 citations

Proceedings Article•DOI•
07 Jun 2004
TL;DR: Simulation experiments show that the critical speed slowdown results in up to 5% energy gains over a leakage oblivious dynamic voltage scaling, and the Procrastination scheduling scheme extends the sleep intervals to 5 times, resulting in an additional 18% energy gain, while meeting all timing requirements.
Abstract: A five-fold increase in leakage current is predicted with each technology generation. While Dynamic Voltage Scaling (DVS) is known to reduce dynamic power consumption, it also causes increased leakage energy drain by lengthening the interval over which a computation is carried out. Therefore, for minimization of the total energy, one needs to determine an operating point, called the critical speed. We compute processor slowdown factors based on the critical speed for energy minimization. Procrastination scheduling attempts to maximize the duration of idle intervals by keeping the processor in a sleep/shutdown state even if there are pending tasks, within the constraints imposed by performance requirements. Our simulation experiments show that the critical speed slowdown results in up to 5% energy gains over a leakage oblivious dynamic voltage scaling. Procrastination scheduling scheme extends the sleep intervals to up to 5 times, resulting in up to an additional 18% energy gains, while meeting all timing requirements.

561 citations


Additional excerpts

  • ...Keywords: leakage power, critical speed, low power scheduling, real-time systems, EDF scheduling, procrastication....

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Journal Article•DOI•
01 Feb 1996
TL;DR: This two-dimensional 8/spl times/8 discrete cosine transform (DCT) core processor for portable multimedia equipment with HDTV-resolution in a 0.3 /spl mu/m CMOS triple-well double-metal technology operates at 150 MHz from a 09 V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3 V DCT.
Abstract: A 4 mm/sup 2/, two-dimensional (2-D) 8/spl times/8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a 0.3-/spl mu/m CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore V/sub DD/-V/sub th/ design space is also studied.

523 citations

Journal Article•DOI•
TL;DR: In this article, the authors present several dual-threshold voltage techniques for reducing standby power dissipation while still maintaining high performance in static and dynamic combinational logic blocks MTCMOS sleep transistor sizing issues are addressed, and a hierarchical sizing methodology based on mutual exclusive discharge patterns is presented.
Abstract: Scaling and power reduction trends in future technologies will cause subthreshold leakage currents to become an increasingly large component of total power dissipation This paper presents several dual-threshold voltage techniques for reducing standby power dissipation while still maintaining high performance in static and dynamic combinational logic blocks MTCMOS sleep transistor sizing issues are addressed, and a hierarchical sizing methodology based on mutual exclusive discharge patterns is presented A dual-V/sub t/ domino logic style that provides the performance equivalent of a purely low-V/sub t/ design with the standby leakage characteristic of a purely high-V/sub t/ implementation is also proposed

473 citations


Cites background from "1-V power supply high-speed digital..."

  • ...Although both pMOS and nMOS gating transistors are shown in Fig....

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Journal Article•DOI•
James W. Tschanz1, Siva G. Narendra1, Y. Ye1, B. Bloechel1, S. Borkar1, Vivek De1 •
27 Oct 2003
TL;DR: In this paper, the authors used dynamic sleep transistors and body bias to control active leakage for a 32-bit integer execution core in 130-nm CMOS technology in order to manage the active power consumption of high-performance digital designs.
Abstract: In order to manage the active power consumption of high-performance digital designs, active leakage control techniques are required to provide significant leakage power savings coupled with fast time constants for entering and exiting idle mode. In this paper, dynamic sleep transistors and body bias are used in conjunction with clock gating to control active leakage for a 32-bit integer execution core in 130-nm CMOS technology. Measurements on pMOS sleep transistor reveal that lowest-leakage state is reached in less than 1 /spl mu/s, resulting in 37/spl times/ reduction in leakage power, while reactivation of block is achieved in less than two clock cycles. PMOS body bias reduces leakage power by 2/spl times/ with no performance penalty, and similar reactivation time. Power measurements at 4 GHz, 1.3 V, 75/spl deg/C demonstrate 8% total power reduction using dynamic body bias and 15% power reduction using a pMOS sleep transistor, for a typical activity profile.

332 citations

References
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Journal Article•DOI•
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Abstract: Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption. >

2,690 citations

Journal Article•
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.
Abstract: Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations This optimum is achieved by trading increased silicon area for reduced power consumption >

2,337 citations

Journal Article•DOI•
Masashi Horiguchi1, Takeshi Sakata1, K. Itoh1•
19 May 1993
TL;DR: In this paper, a switched-source-impedance (SSI) CMOS circuit is proposed as a means of reducing the exponential increase of sub-threshold current with threshold-voltage scaling.
Abstract: A switched-source-impedance (SSI) CMOS circuit is proposed as a means of reducing the exponential increase of subthreshold current with threshold-voltage scaling. Inserting a switched impedance at the source of a MOS transistor reduces the standby subthreshold current of giga-scale LSI's operating at room temperature by three to four orders of magnitude and suppresses the current variation caused by threshold-voltage and temperature fluctuations. The scheme is applicable to any combinational and sequential CMOS logic circuits as long as their standby node voltages are predictable. The standby current of a 16-Gb DRAM is expected to be reduced from 1.1 A to 0.29 mA using this scheme. Hence, battery backup of giga-scale LSI's will be possible even at room temperature and above. >

166 citations

Journal Article•DOI•
Takayuki Kawahara1, Masashi Horiguchi1, Yoshiki Kawajiri1, Goro Kitsukawa1, Tokuo Kure1, Mayu Aoki1 •
01 Jan 1993
TL;DR: In this paper, the authors presented an analytical expression for sub-threshold current reduction in a decoded-driver by self-reverse biasing, which is inherently required for low-voltage, low-power, high-speed DRAM's for portable equipment.
Abstract: Analytical expressions are presented for subthreshold current reduction in a decoded-driver by self-reverse biasing, which is inherently required for low-voltage, low-power, high-speed DRAM's for portable equipment. The scheme involves inserting a switching MOS transistor between the driver circuits and its power supply line. The subthreshold current of the decoded-driver is reduced to the order of 10/sup -3/ in the practical temperature range (250-350 K) with 254 mV of self-reverse biasing voltage, while the delay time is only 3% more than in conventional schemes. The transition time of 1 ms from the operating state to the low subthreshold current state is sufficient to reduce the subthreshold current. The rapid recovery time of 1 ns from the low subthreshold current state does not interrupt the start of normal operation. The subthreshold current reduction was confirmed experimentally using a test chip fabricated with 0.25- mu m technology. >

85 citations

Proceedings Article•DOI•
27 Sep 1993
TL;DR: A 1-V high-speed and low-power digital circuit technology with 0.5/spl mu/m multi-threshold CMOS (MT-CMOS) is proposed, which applies both low-th threshold voltage and high-th thresholds voltage MOSFETs in one LSI.
Abstract: A 1-V high-speed and low-power digital circuit technology with 05/spl mu/m multi-threshold CMOS (MT-CMOS) is proposed This technology applies both low-threshold voltage and high-threshold voltage MOSFETs in one LSI Low-threshold voltage MOSFETs enhance speed performance at a supply voltage of 1 V or less High-threshold voltage MOSFETs suppress the stand-by leakage circuit during the sleep period The technology has achieved logic gate characteristics of a 17-ns propagation delay time and 03-/spl mu/W/MHz/gate power dissipation To demonstrate its effectiveness, a standard cell based PLL-LSI was designed as a carrying vehicle An 18-MHz operation at 1 V was obtained using a 05-/spl mu/m MT-CMOS process >

75 citations