Journal ArticleDOI
10-Gb/s limiting amplifier and laser/modulator driver in 0.18-/spl mu/m CMOS technology
S. Galal,Behzad Razavi +1 more
- Vol. 38, Iss: 12, pp 2138-2146
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TLDR
In this article, a limiting amplifier incorporating active feedback, inductive peaking, and negative Miller capacitance is proposed to achieve a voltage gain of 50 dB, a bandwidth of 9.4 GHz, and a sensitivity of 4.6 mV/sub pp/ for a bit-error rate of 10/sup -12/ while consuming 150 mW.Abstract:
A limiting amplifier incorporates active feedback, inductive peaking, and negative Miller capacitance to achieve a voltage gain of 50 dB, a bandwidth of 9.4 GHz, and a sensitivity of 4.6 mV/sub pp/ for a bit-error rate of 10/sup -12/ while consuming 150 mW. A driver employs T-coil peaking and negative impedance conversion to achieve operation at 10 Gb/s while delivering a current of 100 mA to 25-/spl Omega/ lasers or a voltage swing of 2 V/sub pp/ to 50-/spl Omega/ modulators with a power dissipation of 675 mW. Fabricated in 0.18-/spl mu/m CMOS technology, both prototypes operate with a 1.8-V supply.read more
Citations
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Journal ArticleDOI
A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS Technology
TL;DR: A fully-integrated FMCW radar system for automotive applications operating at 77 GHz has been proposed, using a fractional- synthesizer as the F MCW generator and millimeter-wave PA and LNA incorporated on chip, providing sufficient gain, bandwidth, and sensitivity.
Journal ArticleDOI
Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers
S.. Gondi,Behzad Razavi +1 more
TL;DR: Two equalizer filter topologies and a merged equalizer/CDR circuit are described that operate at 10 Gb/s in 0.13-mum CMOS technology using techniques such as reverse scaling, passive peaking networks, and dual- and triple-loop adaptation.
Proceedings ArticleDOI
A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology
John F. Bulzacchelli,Christian Menolfi,Troy J. Beukema,Daniel W. Storaska,Juergen Hertle,David R. Hanson,Ping-Hsuan Hsieh,Sergey V. Rylov,D. Furrer,Daniele Gardellini,Andrea Prati,Thomas Morf,V. Sharma,R. Kelkar,Herschel A. Ainspan,William R. Kelly,L. R. Chieco,G. A. Ritter,J. A. Sorice,Jon D. Garlett,Robert Callan,Matthias Brandli,P. Buchmann,Marcel Kossel,Thomas Toifl,Daniel J. Friedman +25 more
TL;DR: This paper describes a 28Gb/s serial link transceiver featuring a source-series terminated (SST) driver topology with twice the speed of existing designs, a two-stage peaking amplifier with capacitively-coupled parallel input stages and active feedback, and a 15-tap DFE.
Journal ArticleDOI
40-Gb/s amplifier and ESD protection circuit in 0.18-/spl mu/m CMOS technology
S. Galal,Behzad Razavi +1 more
TL;DR: In this article, a triple-resonance LC network was proposed to increase the bandwidth of cascaded differential pairs by a factor of 2/spl radic/3, yielding a 40-Gb/s CMOS amplifier with a gain of 15 dB and a power dissipation of 190 mW from a 2.2-V supply.
Journal ArticleDOI
CMOS wideband amplifiers using multiple inductive-series peaking technique
TL;DR: In this article, a 10-Gb/s optical transimpedance amplifier (TIA) has been implemented in a 0.18/spl mu/m CMOS process, which accommodates a PD capacitor of 250 fF, achieving the gain of 61 dB/spl Omega/ and 3-dB frequency of 7.2 GHz.
References
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E.M. Cherry,D.E. Hooper +1 more
TL;DR: In this article, a design technique is developed which apparently overcomes all the limitations of common-emitter transistor video amplifiers, based on the use of the impedance mismatch which occurs between stages having alternate series and shunt feedback.
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TL;DR: In this paper, a front-end for a SONET OC-48 (2.5 Gb/s) is presented, where the limiting amplifier (LA) receives a small non-return to zero (NRZ) voltage signal from the transimpedance amplifier (TIA) and amplifies it to a level (e.g. 250 mV/sub pp/) sufficient for the reliable operation of the clock and data recovery circuit.
Journal ArticleDOI
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S. Galal,Behzad Razavi +1 more
TL;DR: In this article, a broadband technique using monolithic T-coils is applied to electrostatic discharge (ESD) structures for both input and output pads, which achieve operation at 10 Gb/s while providing a return loss of -20 dB at 10 GHz.
Journal ArticleDOI
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Journal ArticleDOI
Gigahertz-band high-gain low-noise AGC amplifiers in fine-line NMOS
TL;DR: The design and test results of a single-chip NMOS automatic gain control (AGC) amplifier, capable of operating at 3 GHz with unity gain delivering -8 dBm into a 50-/spl Omega/ load, is described.