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Proceedings ArticleDOI

10Gbps Length adaptive on-chip RF serial link for Network on Chips and Multiprocessor chips applications

17 Jun 2019-pp 1-4
Topics: Spectral efficiency (54%), Radio frequency (52%), Bandwidth (signal processing) (52%), Serial communication (51%), System on a chip (50%)

Summary (2 min read)

Introduction

  • The attenuation is much higher for high frequencies components and causes the pulse traveling through the channel to both decrease in amplitude and spread in time domain.
  • Using both RF and Base band signaling on the same transmission line is possible [5]-[6] to achieve higher data rate than only base band signaling.
  • After this introduction, the system architecture is described in Section II.

B. Main Performance Parameters

  • To simplify the use of serial links in large digital ICs, a length adaptive link is proposed to cover a large range of distances with the same transceiver without any requirement of repeater, thus limiting both power consumption and system complexity.
  • For different link lengths, several parameters vary.
  • For simplification reasons, let us consider a simple cascaded system of a transmitter and the transmission line (attenuation ) only.
  • MODULATION NRZ modulation serial links have been proposed [4]- [5].

A. Duobinary modulation

  • Duo-binary modulation is part of the poly-binary modulations invented by Adam Lender in 1963 [7].
  • It can theoretically double the data rate transmitted through a channel bandwidth BW, where ISI is introduced in a controlled matter to be removed at the reception.
  • In its general form, the duo-binary modulation output bit as defined in equation(2) as the sum of the previous bit 1 and the present bit to be sent.
  • Considering simple duo-binary demodulation, for 200 mV where is the received signal, the received bit is easily distinguishable since it can either take the value 200 mV for a binary “1”, 200 mV for a binary “0”, for 0V the received bit is decided by inverting the previously received bit .
  • Note that the duo-binary modulation compresses the main lobe of the spectrum to half the bandwidth used by NRZ modulation.

B. Differential pre-encoder

  • It can be realized using a XOR logic gate as follows: ⊕ (5) with ⊕ the modulo-2 addition (XOR logic operation).
  • Using this precoding, as shown in the simple scheme in Figure 6, the duo-binary output states becomes binary “0” for 200 mV and binary “1” for 0V.

D. Simulation results

  • The signal states through the system can be seen.
  • Next, is the duo-binary preencoded data used to modulate the 60 GHz carrier, is the modulated signal before self-mixing, and is the received self-mixed signal.
  • In Figure 8, the eye diagram of the system before and after the channel transmission can be seen.
  • To increase the spectral efficiency of the link and relax the RF design constraints, duo-binary modulation was also implemented.

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0Gbps Length adaptive on-chip RF serial link for
Network on Chips and Multiprocessor chips applications
M. Tmimi, S. d’Amico, Jean-Marc Duchamp, Philippe Ferrari, Ph. Galy
To cite this version:
M. Tmimi, S. d’Amico, Jean-Marc Duchamp, Philippe Ferrari, Ph. Galy. 0Gbps Length adaptive
on-chip RF serial link for Network on Chips and Multiprocessor chips applications. International
Conference on IC Design and Technology (ICICDT) 2019, Jun 2019, SUZHOU, France. pp.1-4,
�10.1109/ICICDT.2019.8790923�. �hal-03347157�

10Gbps Length adaptive on-chip RF serial link for Network on Chips and Multi-
processor chips applications
M.Tmimi
1,2
, S. D’Amico
3
,J-M. Duchamp
4
, Ph. Ferrari
2
and Ph.Galy
1
1
STMicroelectronics, 850 rue Jean Monnet, 38920 Crolles FRANCE
2
Univ. Grenoble Alpes, CNRS,Grenoble INP*, RFIC-Lab, F-38000 Grenoble FRANCE
3
Department of Innovation Engineering, University of Salento
4
Univ. Grenoble Alpes, CNRS,Grenoble INP*, G2Elab, F-38000 Grenoble FRANCE
mohammed.tmimi@st.com
Abstract—This paper introduces the use of duo-binary
modulation for a 10-Gbps RF on-chip long range serial link. RF
signaling is used to reduce the delay so that a 5 mm line is
crossed in less than 50 ps. Furthermore, the duo-binary
approach is used to reach higher bandwidth efficiency since this
modulation uses a two-time smaller bandwidth for the
transmission. The RF design complexity is also reduced thanks
to duo-binary modulation.
Keywords-component; RF serial link; duo-binary modulation.
I. INTRODUCTION
Transistor scaling allowed achieving higher density
packing of devices along with faster transistors. However, the
performance of the interconnections did not follow the trend
and is today the main bottleneck for high-speed transceivers
developments. Higher transistor density also implies higher
wires density. In that context, RF link still leads to the best
solution for “on chip” long range connections [1]. However,
wires are more sensible to their environment as compared to
active devices, i.e. closer wires are more sensible to crosstalk
and longer  delay due to wires switching in opposite
polarity for example.
One other main issue in communication systems is
distortion due to the channel physical properties. This might
be due either to the dispersive nature of the channel where the
frequency components propagate at different velocities, or
due to an increase in the attenuation coefficient of the channel
due to the skin effect for example. The attenuation is much
higher for high frequencies components and causes the pulse
traveling through the channel to both decrease in amplitude
and spread in time domain.
Several methods have been carried out in order to solve
these issues. Equalization was used to reduce the frequency
selectivity of the channel by reversing the distortion [2]. Then
reconstructing the original transmitted signal, the coefficients
for the equalizers can be either fixed for a time-invariant
channel using training sequences or after an estimation of the
channel. Otherwise, to reverse the effect of the time-varying
channel an adaptive equalization is required where a known
training sequence is inserted periodically, then algorithms
such as least mean square are used to update the coefficients
of the equalizer [3]. For a fixed channel, to reach higher data
rates, larger bandwidths in the base band have to be equalized,
or more complex modulations such as PAM-4 can be used.
However, several comparators are required for PAM
modulation and more complex filters and algorithms are
required for equalization. Moreover, the complexity and
power consumption of the equalizers dramatically increased
in the last years. The equalization approach was attractive with
the transistor and voltage scaling, which is not optimal
anymore since voltage scaling is slowing down.
Thus the
complexity of the system limits the reachable data rates.
In this work, to answer these issues, an approach inherited
from [4] using a modulated RF carrier and suitable for long-
range links up to several mm length is proposed. For a proof-
of-concept, a 10 Gbps length adaptive serial link for large
digital ICs is designed.
Using both RF and Base band signaling on the same
transmission line is possible [5]-[6] to achieve higher data rate
than only base band signaling. RF-band offers much higher
available bandwidth with low latency. Hence it can be
implemented as a solution for traffic bottlenecks in Network
on Chip (NoC) for example. Herein, a 60-GHz carrier is
proposed to transmit the data. RF transmission line was
chosen because the group delay of the channel is almost
constant over a wide bandwidth. Thus the signal travels at the
same speed that is equal to half the speed of light when
considering standard Back-end-of-lines, leading to low
propagation delay as compared to  delay encountered at
lower frequencies.
Next, to make use of the bandwidth efficiently a pre-
encoded duo-binary modulation [7] is proposed to compress
the spectrum of the signal and thus use a two time smaller
bandwidth. The pre-encoded duo-binary modulation leads to
relaxed design constraints on the RF components compared to
a NRZ modulation. Only half of the NRZ bandwidth is used.
In addition, this duo-binary modulation could be used with a
simple power detector without any local oscillator in the
receiver.
The paper is organized as follows. After this introduction,
the system architecture is described in Section II. Then, the
serial link parameters are outlined in section III. The duo-
binary modulation and differential pre-encoder are detailed in
section IV along with simulation results, and the paper is
concluded in section V.
Authorized licensed use limited to: University of Grenoble Alpes. Downloaded on September 16,2021 at 09:51:44 UTC from IEEE Xplore. Restrictions apply.

II. SYSTEM ARCHITECTURE
The proposed system is described in Figure 1 and is
detailed in this section. The binary data goes through the
differential pre-encoder, which consists in a simple modulo-2
addition. This step is used to cancel the propagation error that
can be introduced by the duo-binary modulation and to
simplify the demodulation. Next the duo-binary encoder
introduces controlled Inter Symbol Interference (ISI) between
the previously sent bit and the present bit to compress the
spectral density closer to the DC. Next the 60-GHz carrier is
modulated and transmitted over differential transmission
lines.
Figure 1. Proposed system architecture.
The proposed approach can be used for both single ended
and differential lines. A differential transmission line was
used herein because it is less sensitive to crosstalk and
electromagnetic interference generated by nearby signals [8].
The amplitude of the received signal depends on both the
transmitted power, which is considered as constant, and the
attenuation of the transmission line, which is proportional to
its length. An RMS power detector is used to demodulate the
received signal and thus generate a 10 Gbps baseband signal
from the received signal. Hence, the generated signal is a
square function of the received signal amplitude. This
operation also allows reducing the number of possible states
from three to two as explained in the following sections.
Finally, the power detector output is compared to a
threshold to generate the data for the following stage.
III. S
ERIAL LINK PARAMETERS
A. Differential Transmission Line used for the Link
On-chip interconnects offer a rather constant propagation
speed at mm-waves, as shown in Figure 2, where a 50-
microstrip line was simulated using the highest metal layer
with the ground in M9 using the 10 Metal layers stack from
STMicroelectronics 28-nm FD-SOI technology. The phase
velocity increases rapidly from few MHz up to about 10 GHz.
Then, from 10 GHz up to 60 GHz, the phase velocity
increases only by 7%, meaning low dispersion.
Hence, for large bandwidth transmissions, a flat group
delay is obtained, leading to reduced distortion and ISI as
compared to a base-band transmission, as mentioned in the
introduction. The transmission line is designed in the BEOL
with SiO
2
substrate with a relative dielectric constant equal to
4, leading to a signal that propagates with half the speed of
light, (i.e. 1.5 10
m/s). Thus 5-mm on-chip length can be
traveled in less than 50 ps.
Furthermore, for an appropriately matched transmission
line, its delay can be linearly related to its length. Hence, the
main characteristics of the propagation channel (attenuation
and delay) are easily predictable and can be anticipated in the
floorplan and design steps of the ICs. For the present case, the
differential microstrip line uses 4.2-um wide strips with a 10-
um spacing, leading to a 1.1-dB/mm attenuation at 60-GHz.
Higher performance could be reached, but at the expense of
larger footprint.
Figure 2. Propagation speed (phase velocity) in a 50- transmission line.
B. Main Performance Parameters
In this work, to simplify the use of serial links in large
digital ICs, a length adaptive link is proposed to cover a large
range of distances with the same transceiver without any
requirement of repeater, thus limiting both power
consumption and system complexity. For different link
lengths, several parameters vary. The most important ones are
the propagation delay, the receiver gain, and the noise figure
of the transmission line, i.e. its insertion loss, which directly
impact the Signal to Noise Ratio (SNR) and Bit Error Rate
(BER) of the system.
For simplification reasons, let us consider a simple
cascaded system of a transmitter (Gain
, and noise figure
) and the transmission line (attenuation
) only. The noise
figure of the cascaded system

can be written as:


󰇛

󰇜
(1)
where
is the noise figure and
is the gain of the
transmitter, respectively, which are considered as constant.
IV. M
ODULATION
NRZ modulation serial links have been proposed [4]-
[5].NRZ is a low-complexity modulation, since the data is
coded into two states, the main disadvantage of this
modulation is its spectral efficiency, as it is not as efficient as
more advanced modulations such as PAM4 or duo-binary
modulations. Duo-binary modulation was considered in this
Authorized licensed use limited to: University of Grenoble Alpes. Downloaded on September 16,2021 at 09:51:44 UTC from IEEE Xplore. Restrictions apply.

work because it has the same spectral efficiency as PAM-4 but
with lower complexity, less comparators and less constraints
on the linearity of the transmitter for example .
A. Duobinary modulation
Duo-binary modulation is part of the poly-binary
modulations invented by Adam Lender in 1963 [7]. It can
theoretically double the data rate transmitted through a
channel bandwidth BW, where ISI is introduced in a
controlled matter to be removed at the reception. In its general
form, the duo-binary modulation output bit
󰇟
󰇠
as defined
in equation(2) as the sum of the previous bit
󰇟
1
󰇠
and
the present bit
󰇟
󰇠
to be sent. It is described in Figure 3.
󰇟
󰇠

󰇟
󰇠

󰇟
1
󰇠
(2)
Figure 3. Duo-binary modulation principle.
A 10 Gbps pseudo-random binary sequence coded in NRZ
where
200 mV was used, as shown in Figure 4. In
time domain, the duo-binary modulation results in an output
signal with three levels, instead of the two levels of NRZ
modulation.
Considering simple duo-binary demodulation, for
200 mV where
is the received signal, the received bit is
easily distinguishable since it can either take the value
200 mV for a binary “1”,
200 mV
for a binary “0”, for
0V the received bit is decided by inverting the previously
received bit
.
Figure 4. Example of duo-binary modulation output in time domain.
The spectral power density is shown in Figure 5. Note that
the duo-binary modulation compresses the main lobe of the
spectrum to half the bandwidth used by NRZ modulation. This
was demonstrated in [7], with equations (3) and (4) giving the
utilized spectrum for duo-binary and NRZ modulations,
respectively.

󰇛

󰇛

󰇜

󰇜
(3)

󰇛

󰇛

󰇜

󰇜
(4)
Figure 5. Power spectral density for NRZ and duo-binary modulations.
B. Differential pre-encoder
The main drawback of duo-binary modulation is the
propagation of an error to the next bits. To avoid this
propagation error, a pre-encoder is required, this precoding is
a modulo-2 addition operation. It can be realized using a XOR
logic gate as follows:
 

⊕ 
(5)
with the modulo-2 addition (XOR logic operation). Using
this precoding, as shown in the simple scheme in Figure 6, the
duo-binary output states becomes binary “0” for
200 mV and binary1” for
0V.
Figure 6. Differential pre-encoder scheme.
C. Self-mixing operation
As mentioned before, a self-mixing operation at the
receiver was used to relax the carrier synchronization where
no PLL or VCO are used at the receiver, furthermore the self-
mixing combined with the previously explained precoding
and duo-binary modulations leads to a simpler demodulation
process.
Before demodulation a three states signal is received:
󰇝∗sin
󰇛
2
󰇜
,0 ,sin
󰇛
2
󰇜
, where
0V refers to a binary “1”, while the two remaining states refer
to binary “0”.
With a self-mixing operation, the number of states after
demodulation can be reduced to two states
󰇝
0 ,
󰇞
only. Hence, the recovered signal can be treated as
Authorized licensed use limited to: University of Grenoble Alpes. Downloaded on September 16,2021 at 09:51:44 UTC from IEEE Xplore. Restrictions apply.

a binary signal that can be compared to a threshold to generate
the required amplitude for the following stage.
D. Simulation results
In Figure 7, simulation results in time domain are shown.
The signal states through the system can be seen. First line,
is the binary data to be sent. Next,
is the duo-binary pre-
encoded data used to modulate the 60 GHz carrier,
is the
modulated signal before self-mixing, and
is the received
self-mixed signal. The retrieved data after demodulation is the
same as the sent data.
Figure 7. Duo-binary modulation output in time domain.
In Figure 8, the eye diagram of the system before and after
the channel transmission can be seen. The simulated SNR is
23.9 dB, which leads to a BER that is lower than 10
-15
.
Figure 8. Duo-binary modulation output eye diagram.
V. CONCLUSION
A 10-Gbps length adaptive serial link was proposed in this
paper. A modulated RF carrier was used to reduce the
propagation delay and simplify the link design. Differential
transmission lines were used to limit cross-talk effects. To
increase the spectral efficiency of the link and relax the RF
design constraints, duo-binary modulation was also
implemented. This modulation has the same spectral
efficiency as PAM-4 without the need for three comparators.
Indeed, the use of a self-mixing process in reception combined
with a differential pre-encoding leads to only two states, thus
only one comparator was required. The simulation showed
that the system exhibits a low BER without code correction
nor equalization. A prototype is under development in ST 28-
nm FDSOI technology.
R
EFERENCES
[1] S. Tam, M. F. Chang, J. Kim and G. Byun, "Wireline/wireless RF-
Interconnect for future SoC," 2011 IEEE International Symposium on
Radio-Frequency Integration Technology, Beijing, 2011, pp. 45-48
[2] Wei Mo, Keng Chen, Yi Liu and Qi Wang, "A 20Gbps on-chip
transceiver with equalization technique for global signal transmission,"
2012 IEEE International Conference on Electron Devices and Solid
State Circuit (EDSSC), Bangkok, 2012, pp. 1-4.
[3] K. J. Wong, E. Chen and C. K. Yang, "Edge and Data Adaptive
Equalization of Serial-Link Transceivers," in IEEE Journal of Solid-
State Circuits, vol. 43, no. 9, pp. 2157-2169, Sept. 2008.
[4] A. P. Jose, G. Patounakis and K. L. Shepard, "Near speed-of-light on-
chip interconnects using pulsed current-mode signalling," Digest of
Technical Papers. 2005 Symposium on VLSI Circuits, 2005., Kyoto,
Japan, 2005, pp. 108-111.
[5] S. Tam, E. Socher, A. Wong and M. F. Chang, "A simultaneous tri-
band on-chip RF-interconnect for future network-on-chip," 2009
Symposium on VLSI Circuits, Kyoto, Japan, 2009, pp. 90-91.
[6] M. Jalalifar and G. Byun, "A 14.4Gb/s/pin 230fJ/b/pin/mm multi-level
RF-interconnect for global network-on-chip communication," 2016
IEEE Asian Solid-State Circuits Conference (A-SSCC), Toyama,
2016, pp. 97-100.
[7] A. Lender, "The duobinary technique for high-speed data
transmission," in Transactions of the American Institute of Electrical
Engineers, Part I: Communication and Electronics, vol. 82, no. 2, pp.
214-218, May 1963.
[8] E. Bogatin , Signal Integrity – Simplified , 2003.
Authorized licensed use limited to: University of Grenoble Alpes. Downloaded on September 16,2021 at 09:51:44 UTC from IEEE Xplore. Restrictions apply.
References
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Q1. What have the authors contributed in "0gbps length adaptive on-chip rf serial link for network on chips and multiprocessor chips applications" ?

This paper introduces the use of duo-binary modulation for a 10-Gbps RF on-chip long range serial link. Furthermore, the duo-binary approach is used to reach higher bandwidth efficiency since this modulation uses a two-time smaller bandwidth for the transmission.