13.2 A 14nm FinFET 128Mb 6T SRAM with V MIN -enhancement techniques for low-power applications
06 Mar 2014-pp 232-233
TL;DR: This paper presents 14nm FinFET-based 128Mb 6T SRAM chips featuring low-VMIN with newly developed assist techniques, and presents peripheral-assist techniques required to overcome the bitcell challenges to high yield.
Abstract: With the explosive growth of battery-operated portable devices, the demand for low power and small size has been increasing for system-on-a-chip (SoC). The FinFET is considered as one of the most promising technologies for future low-power mobile applications because of its good scaling ability, high on-current, better SCE and subthreshold slope, and small leakage current [1]. As a key approach for low-power, supply-voltage (VDD) scaling has been widely used in SoC design. However, SRAM is the limiting factor of voltage-scaling, since all SRAM functions of read, write, and hold-stability are highly influenced by increased variations at low VDD, resulting in lower yield. In addition, the width-quantization property of FinFET device reduces the design window for transistor sizing, and increases the failure probability due to the un-optimized bitcell sizing [1]. In order to overcome the bitcell challenges to high yield, peripheral-assist techniques are required. In this paper, we present 14nm FinFET-based 128Mb 6T SRAM chips featuring low-VMIN with newly developed assist techniques.
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TL;DR: The various SRAM assist schemes are explored to evaluate the power, performance, and area (PPA) gain, and the figure-of-merit (FOM) is induced by the minimum operating voltage (VMIN) and assist overheads.
Abstract: Two 128 Mb 6T SRAM test chips are implemented in a 10 nm FinFET technology A 0040 $\mu \text{m}^{2}$ 6T SRAM bitcell is designed for high density (HD), and 0049 $\mu \text{m}^{2}$ for high performance (HP) The various SRAM assist schemes are explored to evaluate the power, performance, and area (PPA) gain, and the figure-of-merit (FOM) is induced by the minimum operating voltage ( $V_{\mathrm{ MIN}}$ ) and assist overheads The dual-transient wordline scheme is proposed to improve the $V_{\mathrm{ MIN}}$ by 475 mV for the 128 Mb 6T-HP SRAM The suppressed bitline scheme with negative bitline improves the $V_{\mathrm{ MIN}}$ by 135 mV for the 128 Mb 6T-HD SRAM The FOM of PPA gain evaluates the optimum SRAM assist for the different bitcells based on the applications
57 citations
Cites background from "13.2 A 14nm FinFET 128Mb 6T SRAM wi..."
...Compared with the 14 nm FinFET SRAM bitcell [20], the 10 nm FinFET SRAM bitcell demonstrates an area reduction by 38%, the highest density published thus far [20]–[25]....
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...to improve the writability of the selected bitcell [20], [22], [24], [26], thus paving way to create the timing and area overhead for the NBL....
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19 Apr 2015
TL;DR: In this paper, two different SRAM cells, high-performance (HP) and high-density (HD), were irradiated with alpha particles, thermal neutrons, and high energy neutrons.
Abstract: Radiation-induced Soft Error Rate (SER) of SRAM built in 14nm FinFET on bulk technology was extensively characterized. Two different SRAM cells, high-performance (HP) and high-density (HD), were irradiated with alpha particles, thermal neutrons, and high-energy neutrons. Empirical results reveal excellent SER performance of FinFET compared to the prior technology nodes, drastically reducing SER FIT rate by 5–10X. It is found that HP cell is more sensitive to a single event upset than HD cell design. We will discuss the effects of charge collection efficiency as one of major parameter and present supporting simulation results.
57 citations
TL;DR: Trends in the design of device and circuits for on-chip nonvolatile memory using memrisitive devices as well as the challenges faced by researchers in its further development are examined.
Abstract: Memristive devices have shown considerable promise for on-chip nonvolatile memory and computing circuits in energy-efficient systems. However, this technology is limited with regard to speed, power, VDDmin, and yield due to process variation in transistors and memrisitive devices as well as the issue of read disturbance. This paper examines trends in the design of device and circuits for on-chip nonvolatile memory using memristive devices as well as the challenges faced by researchers in its further development. Several silicon-verified examples of circuitry are reviewed in this paper, including those aimed at high-speed, area-efficient, and low-voltage applications.
51 citations
01 Dec 2017
TL;DR: A fully integrated 7nm CMOS platform featuring a 3rd generation finFET architecture, SAQP for fin formation, and SADP for BEOL metallization, designed to enable both High Performance Compute (HPC) and mobile applications.
Abstract: We present a fully integrated 7nm CMOS platform featuring a 3rd generation finFET architecture, SAQP for fin formation, and SADP for BEOL metallization. This technology reflects an improvement of 2.8X routed logic density and >40% performance over the 14nm reference technology described in [1-3]. A full range of Vts is enabled on-chip through a unique multi-workfunction process. This enables both excellent low voltage SRAM response and highly scaled memory area simultaneously. The HD 6-T bitcell size is 0.0269um2. This 7nm technology is fully enabled by immersion lithography and advanced optical patterning techniques (like SAQP and SADP). However, the technology platform is also designed to leverage EUV insertion for specific multi-patterned (MP) levels for cycle time benefit and manufacturing efficiency. A complete set of foundation and complex IP is available in this advanced CMOS platform to enable both High Performance Compute (HPC) and mobile applications.
50 citations
TL;DR: In this paper, the authors investigated the difference between planar and FinFET devices in terms of soft error rate (SER) and found that the reduction in sensitivity of planar MOSFETs is primarily due to an increase in the threshold LET and a reduction in the sensitive volume due to the shape of the transistor.
Abstract: The assessment of the soft-error rate (SER) of semiconductor devices continues to be important, even with the adoption of FinFET devices which overcome some important limitations of planar MOSFETs. The study in this paper presents both theoretical and experimental results via advanced simulation techniques, to investigate the difference between planar and FinFET devices in terms of SER. Neutron test results from different facilities are presented, and the observed differences in sensitivity are explained through theoretical analysis. In the second half of the paper, the test results are validated through TCAD and TFIT simulations using a calibrated technology response model. The analysis shows that the reduction in sensitivity of FinFET devices is primarily due to an increase in the threshold LET and a reduction in the sensitive volume due the shape of the transistor.
49 citations
References
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IBM1
TL;DR: For both low-power and high-performance applications, DGCMOS-FinFET offers a most promising direction for continued progress in VLSI.
Abstract: Double-gate devices will enable the continuation of CMOS scaling after conventional scaling has stalled. DGCMOS/FinFET technology offers a tactical solution to the gate dielectric barrier and a strategic path for silicon scaling to the point where only atomic fluctuations halt further progress. The conventional nature of the processes required to fabricate these structures has enabled rapid experimental progress in just a few years. Fully integrated CMOS circuits have been demonstrated in a 180 nm foundry-compatible process, and methods for mapping conventional, planar CMOS product designs to FinFET have been developed. For both low-power and high-performance applications, DGCMOS-FinFET offers a most promising direction for continued progress in VLSI.
413 citations
03 Apr 2012
TL;DR: A high-performance, voltage-scalable 162Mb SRAM array is developed in a 22nm tri-gate bulk technology featuring 3rd-generation high-k metal-gate transistors and 5th-generation strained silicon to address process variation and fin quantization at 22nm.
Abstract: Future product applications demand increasing performance with reduced power consumption, which motivates the pursuit of high-performance at reduced operating voltages. Random and systematic device variations pose significant challenges to SRAM V MIN and low-voltage performance as technology scaling follows Moore's law to the 22nm node. A high-performance, voltage-scalable 162Mb SRAM array is developed in a 22nm tri-gate bulk technology featuring 3rd-generation high-k metal-gate transistors and 5th-generation strained silicon. Tri-gate technology reduces short-channel effects (SCE) and improves subthreshold slope to provide 37% improved device performance at 0.7V. Continuous device width sizing in planar technology is replaced by combining parallel silicon fins to multiply drive current. Process-circuit co-optimization of transient voltage collapse write assist (TVC-WA) and wordline underdrive read assist (WLUD-RA) features address process variation and fin quantization at 22nm and enable a 175mV reduction in the supply voltage required for 2GHz SRAM operation. Figure 13.1.1 shows an SEM top-down view of a 0.092μm2 high-density 6T SRAM bitcell (HDC) and a 0.108μm2 low-voltage 6T SRAM cell (LVC) after gate and diffusion processing. Computational OPC/RET techniques extend the capabilities of 193nm immersion lithography to allow a 1.85× increase in array density relative to 32nm designs [1].
177 citations
TL;DR: A high-performance low-power 153 Mb SRAM is developed in 45 nm high-k Metal Gate technology with Dynamic SRAM PMOS forward-body-bias and Active-Controlled SRAM VCC in Sleep integrated in the design to lower Active-VCCmin and Standby Leakage, respectively.
Abstract: A high-performance low-power 153 Mb SRAM is developed in 45 nm high-k Metal Gate technology. Dynamic SRAM PMOS forward-body-bias (FBB) and Active-Controlled SRAM VCC in Sleep are integrated in the design to lower Active-VCCmin and Standby Leakage, respectively. FBB improves the Active-VCCmin by up to 75 mV, and Active-Controlled SRAM VCC distribution tightened by 100 mV, both of which result in further power reduction. A 0.346 mum2 6T-SRAM bit-cell is used which is optimized for VCCmin, performance, leakage and area. The design operates at high-speed over a wide voltage range, and has a maximum frequency of 3.8 GHz at 1.1 V. The 16 KB Subarray was also used as the building block in on-die 6 MB Cache for Intel Core 2 Duo CPU in 45 nm technology.
96 citations
29 May 2009
TL;DR: A 512Kb dual-power-supply SRAM is fabricated in 40nm CMOS with 0.179µm2 cell, which is 10% smaller than the SRAM scaling trend, and an adaptive WL level-control scheme generated from dual power supplies in the WL driver increases SRAM operating margin.
Abstract: A 512Kb dual-power-supply SRAM is fabricated in 40nm CMOS with 0.179µm2 cell, which is 10% smaller than the SRAM scaling trend. The smaller cell size is realized by channel area saving. To improve the cell stability of the small channel area cell, we use a WL level-control scheme generated from dual power supplies in the WL driver. An adaptive WL-level programming scheme and dynamic-array-supply control increase SRAM operating margin. As a result, the cell failure rate is improved more than three orders of magnitude compared to the conventional dual-power-supply SRAM.
93 citations
IBM1
TL;DR: A 64 Mb SRAM macro has been fabricated in a 32 nm high-k metal-gate SOI technology with improved stability and performance and a bit-cell-tracking delay circuit improves both performance and yield across the process space.
Abstract: A 64Mb SRAM macro is fabricated in a 32nm high-k metal-gate (HKMG) SOI technology [1]. Figure 14.1.1 shows the 0.154μm2 bitcell (BC). A 2× size reduction from the previous 45nm design [2] is enabled by an equal 2× reduction in BC area. No corner rounding of BC gates allows tighter overlay of gate electrode and active area. The introduction of HKMG provides a significant reduction in the equivalent oxide thickness, thereby reducing the Vt mismatch. This reduction allows aggressive scaling of device dimensions needed to achieve the small area footprint. A 0.7V VDD MIN operation is enabled by three assist features. Stability is improved by a bitline (BL) regulation scheme. Enhancements to the write path include an increase of 40% of BL boost voltage. Finally, a BC-tracking delay circuit improves both performance and yield across the process space.
90 citations