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Proceedings ArticleDOI

16*16 limited intermediate buffer switch module for ATM networks

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TLDR
An investigation is made of the performance of a nonblocking packet switch having input buffers and a limited amount of buffers within the switch fabric, where contention for the output ports occurs, and it is suggested that for unbalanced and bursty traffic, theperformance of the switch does not degrade appreciably.
Abstract
An investigation is made of the performance of a nonblocking packet switch having input buffers and a limited amount of buffers within the switch fabric, where contention for the output ports occurs. This technique improves the performance significantly, while maintaining the switch fabric speed equal to that of the port speed. For uniform traffic, a 16*16 switch with head of line priority scheduling has an achievable throughput equal to 87.5%. The simulation results suggest that for unbalanced and bursty traffic, the performance of the switch does not degrade appreciably. >

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Citations
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Proceedings ArticleDOI

CIXB-1: combined input-one-cell-crosspoint buffered switch

TL;DR: This work proposes a novel architecture: a combined input-one-cell-crosspoint buffer crossbar (CIXB-1) with virtual output queues (VOQs) at the inputs and round-robin arbitration that can provide 100% throughput under uniform traffic.
Proceedings ArticleDOI

CIXOB-k: combined input-crosspoint-output buffered packet switch

TL;DR: A novel architecture, a combined input-crosspoint-output buffered (CIXOB-k, where k is the size of the crosspoint buffer) Switch, which provides 100% throughput under uniform and unbalanced traffic and provides timing relaxation and scalability.
Journal ArticleDOI

MCBF: a high-performance scheduling algorithm for buffered crossbar switches

TL;DR: This work proposes a novel scheduling scheme named the most critical buffer first (MCBF), which is based only on the internal buffer information and requires much less hardware than the existing schemes and exhibits good performance and outperforms all its competitors.
Journal ArticleDOI

An evolution to crossbar switches with virtual output queuing and buffered cross points

TL;DR: This tutorial article presents an overview of switch matrix scheduling for VOQ IQ switches with crossbar switch fabrics, and shows how CICQ switches have simple schedulers and result in lower delay than IQ switches, both of which have unstable regions.
Journal ArticleDOI

A four-terabit packet switch supporting long round-trip times

TL;DR: This 4-TBPS packet switch uses a combined input- and crosspoint-queued (CICQ) structure with virtual output queuing at the ingress to achieve the scalability of input-buffered switches, the performance of output-buffering switches, and low latency.
References
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Journal ArticleDOI

Input Versus Output Queueing on a Space-Division Packet Switch

TL;DR: Two simple models of queueing on an N \times N space-division packet switch are examined, and it is possible to slightly increase utilization of the output trunks and drop interfering packets at the end of each time slot, rather than storing them in the input queues.
Journal ArticleDOI

Queueing in high-performance packet switching

TL;DR: In this article, the authors study the performance of four different approaches for providing the queuing necessary to smooth fluctuations in packet arrivals to a high-performance packet switch, including input queuing, smoothing, output queuing and completely shared buffering.
Book

The Knockout Switch: a simple, modular architecture for high-performance packet switching

TL;DR: A new, high-performance packet-switching architecture, called the Knockout Switch, is proposed, which uses a novel concentrator design at each output to reduce the number of separate buffers needed to receive simultaneously arriving packets.
Journal ArticleDOI

The Knockout Switch: A Simple, Modular Architecture for High-Performance Packet Switching

TL;DR: The Knockout Switch as discussed by the authors uses a fully interconnected switch fabric topology (i.e., each input has a direct path to every output) so that no switch blocking occurs where packets destined for one output interfere with (block or delay) packets going to different Outputs.
Journal ArticleDOI

Fast packet switch architectures for broadband integrated services digital networks

TL;DR: In this article, three basic types of packet switches are identified: the shared-memory, shared-medium, and space-division types, and a set of definitions and a brief description of the functionality required of fast packet switches is given.
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