16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter
01 Feb 2020-pp 260-262
TL;DR: Digitizing near-GHz RF BW with a typical oversampling ratio (OSR) of ~16 requires a very high sampling frequency with prohibitive power dissipation even in advanced process nodes, and the power consumption and area penalties can be prohibitive.
Abstract: Modern wireless communication systems operating at tens of GHz have opened a near-GHz contiguous RF BW for various applications. Further, spectral efficiency has often necessitated such applications to use MIMO and beamforming, resulting in systems that are highly integrated and require tight power budgets. The ADC, being an indispensable element of these systems, has been thus pushed to digitize ever-increasing BWs (>500MHz) with low power dissipation and area, in an integration-friendly manner. Continuous-time (CT) ΔΣ ADCs have traditionally been used in integrated receiver applications because their oversampling and inherent anti-aliasing ease the frequency planning and make on-chip active filtering possible. Designing these CT ΔΣ ADCs for BW specifications of more than 500MHz, however, is challenging. Digitizing near-GHz RF BW with a typical oversampling ratio (OSR) of ~16 requires a very high sampling frequency with prohibitive power dissipation even in advanced process nodes. Using discrete-time (DT) ADCs is a possibility, but the ADC will still need to be oversampled to ease on-chip filtering and to prevent unwanted mixer terms from aliasing in-band. Thus, the power consumption and area penalties can be prohibitive.
Citations
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Xidian University1, Fudan University2, Beihang University3, Peking University4, Chinese Academy of Sciences5, Tsinghua University6, University of Science and Technology of China7, Nanjing Tech University8, University of Electronic Science and Technology of China9, Nanjing University10, Tianjin Polytechnic University11, Southwest Jiaotong University12
TL;DR: In this article, the authors reviewed the recent progress of integrated circuits and optoelectronic chips and focused on the research status, technical challenges and development trend of devices, chips, and integrated technologies of typical IC and Optoelectronics chips.
Abstract: Integrated circuits (ICs) and optoelectronic chips are the foundation stones of the modern information society. The IC industry has been driven by the so-called “Moore’s law” in the past 60 years, and now has entered the post Moore’s law era. In this paper, we review the recent progress of ICs and optoelectronic chips. The research status, technical challenges and development trend of devices, chips and integrated technologies of typical IC and optoelectronic chips are focused on. The main contents include the development law of IC and optoelectronic chip technology, the IC design and processing technology, emerging memory and chip architecture, brain-like chip structure and its mechanism, heterogeneous integration, quantum chip technology, silicon photonics chip technology, integrated microwave photonic chip, and optoelectronic hybrid integrated chip.
30 citations
TL;DR: The continuous-time pipelined (CTP) ADC as discussed by the authors is an emerging analog-to-digital converter that combines anti-alias filtering and quantization in a single unit.
Abstract: The continuous-time pipelined(CTP) ADC is an emerging analog-to-digital converter that combines anti-alias filtering and quantization in a single unit. It presents a resistive input impedance making it easy to drive, and places relaxed requirements on amplifiers used in the ADC. The CTP ADC attempts to address many of the challenges of discrete-time pipelined analog-to-digital conversion. This brief is a first-principles introduction to this recent architecture.
18 citations
TL;DR: This long review paper summarizes and discusses recent trending IC design directions and challenges, and tries to give the readers big/cool pictures on each selected small/hot topics.
Abstract: For the non-stop demands for a better and smarter society, the number of electronic devices keeps increasing exponentially; and the computation power, communication data rate, smart sensing capability and intelligence are always not enough. Hardware supports software, while the integrated circuit (IC) is the core of hardware. In this long review paper, we summarize and discuss recent trending IC design directions and challenges, and try to give the readers big/cool pictures on each selected small/hot topics. We divide the trends into the following six categories, namely, 1) machine learning and artificial intelligence (AI) chips, 2) communication ICs, 3) data converters, 4) power converters, 5) imagers and range sensors, 6) emerging directions. Hope you find this paper useful for your future research and works.
14 citations
TL;DR: This follow-up article describes and compares the main time-encoding architectures for analog-to-digital converters (ADCs) and discusses the corresponding design challenges of the circuit blocks.
Abstract: The scaling of CMOS technology deep into the nanometer range has created challenges for the design of highperformance analog ICs: they remain large in area and power consumption in spite of process scaling. Analog circuits based on time encoding [1], [2], where the signal information is encoded in the waveform transitions instead of its amplitude, have been developed to overcome these issues. While part one of this overview article [3] presented the basic principles of time encoding, this follow-up article describes and compares the main time-encoding architectures for analog-to-digital converters (ADCs) and discusses the corresponding design challenges of the circuit blocks. The focus is on structures that avoid, as much as possible, the use of traditional analog blocks like operational amplifiers (opamps) or comparators but instead use digital circuitry, ring oscillators, flip-flops, counters, an so on. Our overview of the state of the art will show that these circuits can achieve excellent performance. The obvious benefit of this highly digital approach to realizing analog functionality is that the resulting circuits are small in area and more compatible with CMOS process scaling. The approach also allows for the easy integration of these analog functions in systems on chip operating at "digital" supply voltages as low as 1V and lower. A large part of the design process can also be embedded in a standard digital synthesis flow.
13 citations
Cites background from "16.6 An 800MHz-BW VCO-Based Continu..."
...REFERENCE [55] [20] [25] [41] [19] [10] [8] [34] [38] [9]...
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...Input Feedforward Architectures An alternative for closed-loop operation is the input feedforward architecture (also known as the coarse/ fine structure) [17]–[20]....
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...A close second is the work in [20], which is a true oversampling converter with an effective application bandwidth of 800 MHz and approximately 10 effective bits resolution....
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08 Apr 2021
TL;DR: A three-stage continuous-time pipeline ADC that achieves 70-dB SNDR in a 100-MHz bandwidth while sampling at 800 MHz is described, implemented in 65-nm CMOS.
Abstract: We describe the design principles and circuit details of a three-stage continuous-time pipeline (CTP) ADC that achieves 70-dB SNDR in a 100-MHz bandwidth while sampling at 800 MHz Implemented in 65-nm CMOS, the ADC is easy to drive and incorporates an inherent anti-alias filter that achieves 60-dB rejection in the first Nyquist band Each pipeline stage is realized using a second-order Rauch-filter-based residue amplifier that incorporates a 9-level resistive DAC and an RC-delay line A dummy-switching scheme relaxes DAC reference-buffer requirements The back-end ADC is a $4\times $ time-interleaved 7-bit SAR converter The Schreier and Walden FoMs of our ADC are 1654 dB and 561 fJ/level, respectively
11 citations
Cites background or methods or result from "16.6 An 800MHz-BW VCO-Based Continu..."
...A possible way of implementing an on-chip calibration engine is given in [2]....
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...A continuous-time pipeline (CTP) converter is an emerging architecture [1], [2] that avoids the need to close the sampled-data feedback loop that is needed in a CTDSM....
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...This is in contrast to prior art designs [1], [2], [6] that employ currentsteering techniques, which necessitated an additional higher supply to achieve an adequately low noise....
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...Like in [2], this is an improvement over earlier work that uses a first-order residue amplifier [1]....
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References
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TL;DR: This paper presents a second-generation mostly-digital background-calibrated oversampling ADC based on voltage- controlled ring oscillators (VCROs) that is in line with the best ΔΣ modulator ADCs published to date, but it occupies much less circuit area, is reconfigurable, and consists mainly of digital circuitry.
Abstract: This paper presents a second-generation mostly-digital background-calibrated oversampling ADC based on voltage- controlled ring oscillators (VCROs). Its performance is in line with the best ΔΣ modulator ADCs published to date, but it occupies much less circuit area, is reconfigurable, and consists mainly of digital circuitry. Enhancements relative to the first-generation version include digitally background-calibrated open-loop V / I conversion in the VCRO to increase ADC bandwidth and enable operation from a single low-voltage power supply, quadrature coupled ring oscillators to reduce quantization noise, digital over-range correction to improve dynamic range and enable graceful overload behavior, and various circuit-level improvements. The ADC occupies 0.075 mm2 in a 65 nm CMOS process and operates from a single 0.9-1.2 V supply. Its sample-rate is tunable from 1.3 to 2.4 GHz over which the SNDR spans 70-75 dB, the bandwidth spans 5-37.5 MHz, and the minimum SNDR+ 10log(bandwidth/power dissipation) figure of merit (FOM) is 160 dB.
90 citations
"16.6 An 800MHz-BW VCO-Based Continu..." refers background or methods in this paper
...The limited NSD, SFDR, and anti-aliasing of the VCO ADC are enhanced by the preceding CT pipeline stage....
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...The 160-level signal from the VCO ADC is further converted into a 15b signal through a LUT that performs nonlinearity correction and is then provided to the reconstruction filter....
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...A CT VCO ADC is another candidate that provides inherent anti-aliasing with low analog circuit complexity [2]....
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...The anti-aliasing of the ADC is provided by the combination of the 2nd-order inter-stage low-pass filter and the sinc STF of the CT VCO ADC [2]....
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...In the VCO ADC core, 10 three-stage ring oscillators are connected in a phase-interpolated manner to increase the number of quantization levels....
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TL;DR: An oversampled continuous-time (CT) pipeline ADC clocked at 9 GHz achieving 1.125-GHz bandwidth and −164 dBFS/Hz average small-signal noise density is presented.
Abstract: An oversampled continuous-time (CT) pipeline ADC clocked at 9 GHz achieving 1.125-GHz bandwidth and −164 dBFS/Hz average small-signal noise density is presented. In contrast to traditional discrete-time (DT) pipeline ADCs, the system processes the signals in CT form throughout all the pipeline stages and thus sampling-induced artifacts such as aliasing and high-peak ADC driving current are mitigated. Despite the oversampled nature of the ADC, its digitization bandwidth is on par with that of traditional non-interleaved DT pipeline ADCs since CT signal processing is not constrained by settling time requirements. The ADC was fabricated in a 28-nm CMOS process technology and consumes 2.3 W.
43 citations
"16.6 An 800MHz-BW VCO-Based Continu..." refers background in this paper
...However, a straightforward implementation results in high power consumption due to the large number of stages needed to achieve sufficiently low noise-spectral density (NSD) and the associated digital signal processing supporting the high number of stages [1]....
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...6, only [1] and this work achieve more than 500MHz application BW together with better than −70dBc THD and 70dB SFDR, typically required by high-performance wireless applications....
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...A CT pipelined ADC is attractive due to its low-OSR operation together with inherent anti-aliasing [1]....
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...Further, this ADC dissipates 8× lower power and occupies 15× lower area than that of [1], while fully integrating the DRF and its coefficient calibration hardware....
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01 Feb 2017
TL;DR: This paper describes an 8GS/s 16-way time-interleaved ADC for a test and measurement application that uses the split-capacitor switching scheme to provide a constant common mode to the comparator during conversion.
Abstract: This paper describes an 8GS/s 16-way time-interleaved ADC for a test and measurement application. Each ADC slice is a 1b/cycle, synchronous SAR operating at 500MS/s. The ADC slice schematic is shown in Fig. 16.5.1. The input is sampled using a thick-oxide NFET driven by a 1.9V buffer. After each conversion the hold node is reset differentially using a core NFET driven by a 1.1V buffer. The 10b DAC consists of two identical 5b halves separated by a bridging capacitor, C bridge . C bridge is sized to provide approximately 0.8b of redundancy between the MSB and LSB halves, enabling capacitor mismatch in the MSB half to be corrected digitally. The DAC is controlled by decision latches and uses the split-capacitor switching scheme [1] to provide a constant common mode to the comparator during conversion. The DAC comprises approximately 60% of the 250fF/side hold capacitance, resulting in a 1.2V ppd full-scale range when a 1V reference is used.
29 citations
01 Feb 2019
TL;DR: This paper presents a meta-modelling architecture suitable for directly digitizing wide bandwidth (BW) signals with high spectral purity at low power consumption, using either time-interleaved or pipelined architectures.
Abstract: Emerging 5G communication systems require ADCs to directly digitize wide bandwidth (BW) signals with high spectral purity at low power consumption. Current state-of-the-art solutions include mainly time-interleaved (TI) pipelined [1–4] or pipelined-SAR [5] architectures, enhanced by digital calibration. To ensure a sufficiently high input BW, all these designs employ a static front-end buffer. This buffer often dissipates more power than the ADC itself, significantly deteriorates the linearity and noise performance, and severely limits the available swing, unless over-voltage or multiple supplies are used [1–5].
12 citations