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1995 ieee international so1 conference proceedings

About: The article was published on 1995-01-01 and is currently open access. It has received None citations till now.
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Proceedings ArticleDOI
03 Oct 1995
TL;DR: In this article, a large-signal SOI MOSFET model with self-heating effects is presented, which is suitable for SOI monolithic microwave ICs.
Abstract: This paper presents a large-signal SOI MOSFET model which explicitly includes self-heating effects. Our goal is to develop a model suitable for SOI monolithic microwave IC (MMIC) design which clearly requires a large-signal model accurate at high frequencies. In addition, the model must include the dynamic thermal response of the device since MMICs often contain microwave, RF, baseband, and bias sections spanning the range from DC to several GHz. At DC, self-heating can be modeled with a simple thermal resistance, while at microwave frequencies the temperature is effectively constant. However, at intermediate frequencies the temperature lags the applied power so the model must accurately represent the thermal dynamics in the device.

5 citations

Proceedings ArticleDOI
H. Kikuchi1, T. Hamajima1, K. Kobayashi, M. Takashi, K. Arai 
03 Oct 1995
TL;DR: In this article, an improved fabrication process of poly-Si sandwiched bonded (PSB) structures without Sb diffusion into polySi layers is proposed, and a new SOI structure with gaps fabricated by a wafer direct bonding technique.
Abstract: Intelligent power ICs with vertical double-diffused MOS (VDMOS) output devices are used for solenoid controlled applications. Many structures have been proposed for these power ICs. We have developed poly-Si sandwiched bonded (PSB) structures which use a Sb doped poly-Si and crystal-Si bonding technique. However these PSB structures have a high fabrication cost, because the fabrication process includes Sb diffusion into poly-Si layers. In this paper, we first propose an improved fabrication process of PSB structures without Sb diffusion into poly-Si layers. Second, we propose a new SOI structure with gaps fabricated by a wafer direct bonding technique. Both structures enable us to obtain low-cost intelligent power ICs with VDMOS.

4 citations

Proceedings ArticleDOI
03 Oct 1995
TL;DR: In this paper, a unique set of carrier lifetime and impact ionization rate can be used to account for both the transient behavior and DC I-V characteristics of a partially-depleted SOI MOSFET.
Abstract: This paper has shown that a unique set of carrier lifetime and impact ionization rate can be used to account for both the transient behavior and DC I-V characteristics of a partially-depleted SOI MOSFET. Operation of these devices at low to moderate drain voltages ( 1.0 to 2.0 V) was shown to be strongly related to both impact ionization rate and carrier lifetime.

3 citations