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Journal ArticleDOI

2-D Analytical Modeling of Surface Potential and Threshold Voltage for Vertical Super-Thin Body FET

01 May 2017-IEEE Transactions on Electron Devices (Institute of Electrical and Electronics Engineers (IEEE))-Vol. 64, Iss: 5, pp 2106-2112
TL;DR: In this paper, a 2D analytical model for surface potential and threshold voltage of novel vertical super-thin body (VSTB) FET has been derived by solving 2-D Poisson equation.
Abstract: In this paper, a 2-D analytical model for surface potential and threshold voltage of novel vertical super-thin body (VSTB) FET has been derived by solving 2-D Poisson equation. The analytical surface potential expression for gate-side surface and sidewall side surface has been modeled using parabolic surface potential approximation. The threshold voltage model for the VSTB FET has been derived by applying strong inversion criterion at the surface potential minimum value. The threshold voltage model for the VSTB FET has been analyzed by varying the body thickness, oxide thickness, and channel doping concentrations. The drain-induced barrier lowering and threshold voltage roll-off parameters are also extracted and analyzed for different body thicknesses. The models for surface potential and threshold voltage have been compared with the results obtained from the 2-D numerical device simulator and a very good agreement between the two has been observed.
Citations
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Journal ArticleDOI
TL;DR: In this article, a simulation-based performance study of vertical super-thin body (VSTB) MOSFET vis-a-vis various other MOS devices was presented.
Abstract: In this work, a simulation-based performance study of vertical super-thin body (VSTB) MOSFET vis-a-vis various other MOS devices was presented. Use of appropriate doping profile greatly improves on to off current ratio (ION/IOFF) and subthreshold swing (SS). Improvement in input characteristics (ID–VGS) by gate–source (G/S) and gate–drain (G/D) overlap technique was explained with the help of electron density, mobility, and velocity of the device in off and on-states. Device performance shows negligible deviations in presence of different effects like stress, strain, tunneling, and velocity saturation. VSTB FET supports the downscaling of device size by offering excellent electrostatic integrity and low supply voltage operation. Values of off-current (IOFF), peak on-current (ION), peak transconductance (gm), SS, and DIBL for channel length (L) of 20 nm are 0.00145 nA/µm, 327.85 µA/µm, 974 µS/µm, 65.1 mV/dec, and 39.6 mV/V, respectively. Noise impact on device performance for three different noise sources (diffusion, generation–recombination/G–R, and flicker noise) was studied at two different frequencies (f = 1 MHz and 10 GHz). Maximum values of unit-gain cut-off frequencies (fTmax) obtained for channel lengths (L) of 20, 25, and 30 nm are 86.26, 80.47, and 76.22 GHz, respectively.

14 citations

Journal ArticleDOI
TL;DR: In this article, surface potential and drain current models for a physically based double halo metal-oxide-semiconductor-field effect transistor (MOSFET) are reported, where the conventional silicon-dioxide (SiO2) material is replaced with a promising high-k dielectric material hafnium oxide (HfO2).
Abstract: Surface potential and drain current models for a physically based double halo metal–oxide–semiconductor-field-effect-transistor (MOSFET) are reported. The proposed models have been established in sub-threshold mode of MOSFET operation. The depletion layer depth used in the pseudo two dimensional Poisson’s equation comprises the effect of two symmetrical pocket implantations at both the ends of the channel region. In this effort, improvement in the investigation is brought in by taking lateral asymmetric channel owing to non-uniform doping. The conventional silicon-dioxide (SiO2) material is replaced with a promising high-k dielectric material hafnium oxide (HfO2) to analyze the surface potential and drain current models. Analytical results have been compared using Synopsys technology computer aided design (TCAD). Excellent conformities between the analytical models and simulations are observed.

11 citations

Journal ArticleDOI
TL;DR: In this paper, the authors investigated trap concentration (TC) of 1013 eV−1.cm−2 with different trap distributions (uniform and Gaussian) and concentrations using TCAD tools.
Abstract: We investigated vertical super-thin body (VSTB) FET performance in presence of different interface (HfO2/Si) trap distributions (uniform and Gaussian) and concentrations using TCAD tools. For trap concentration (TC) of 1013 eV−1 cm−2, the percentage change in on-to-off current ratio (Ion/Ioff) is 93.91% for uniform trap (UT) and 49.8% for Gaussian trap (GT) distribution. For the same TC, subthreshold swing (SS) shows percentage change of 5.1% for UT and 11.41% for GT distribution. Thus, the device performance shows good immunity for TC up to 1013 eV−1 cm−2. However, for TC = 1014 eV−1 cm−2 SS degrades significantly. The influence of traps on the cumulative effect of three noise sources (diffusion + generation–recombination/G–R + flicker) and on individual noise sources (G–R and diffusion) is explained qualitatively at low and high frequencies (f = 1 MHz and 10 GHz). The study shows that the overall noise cannot disturb the device performance at very high frequency. Various radio-frequency (RF) parameters like transconductance (gm), total input capacitance (Cgg), gate-drain capacitance (Cgd), unit-gain cutoff frequency (fT), and gain–bandwidth-product (GBP) are also studied for variation of trap types. For TC = 1014 eV−1 cm−2, the percentage change in fTmax (GBPmax) is − 21.43% (− 8%) for UT and − 22.86% (− 9.6%) for GT distribution.

10 citations

Journal ArticleDOI
01 Jun 2021-Silicon
TL;DR: In this paper, a simulation study of the influence of temperature on the performance of dual material gate (DMG) vertical super-thin body (VSTB) FET is presented.
Abstract: This work presents a simulation study of the influence of temperature on the performance of dual material gate (DMG) vertical super-thin body (VSTB) FET. The introduction of DMG causes a drop in the off-state current (Ioff) by ~99.18% and DIBL by 20%. Drop in the Ioff enhances the on-to-off current ratio (Ion/Ioff) by ~98.85%. A rigorous investigation on temperature dependency of DC, analog/RF, and linearity metrics was carried out. The zero temperature coefficient (ZTC) bias point for the DMG device was observed to be nearly at a gate bias of VG = 0.41 V. Various DC figures of merit (FoM) such as subthreshold swing (SS), Ion/Ioff, and threshold voltage (VT) show improvement with temperature fall. Lowering in temperature also leads to enhanced analog/RF performance by offering superior gm, gd, Cgg, Cgd, maximum fT, maximum GBP, intrinsic delay, TGF, TFP, GFP, and GTFP. However, linearity metrics like gm2, gm3, VIP2, VIP3, IIP3, IMD3, and 1-dB compression point show better performance with an increase in temperature.

8 citations


Cites methods from "2-D Analytical Modeling of Surface ..."

  • ...Various analytical modeling based works for VSTB FET have also been developed [10, 11]....

    [...]

Journal ArticleDOI
TL;DR: In this article, a two dimensional analytical model of the proposed dual material (DM) Vertical Super Thin Body (VSTB) strained Field Effect Transistor (FET) with focus on its short channel behaviour in nanometer regime was developed.

7 citations

References
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Journal ArticleDOI
TL;DR: In this article, the authors focused on scaling CMOS to its fundamental limits, determined by manufacturing, physics, and costs using new materials and nonclassical structures using new non-classical CMOS structures.
Abstract: The rapid cadence of metal-oxide semiconductor field-effect transistor (MOSFET) scaling, as seen in the new 2003 International Technology Roadmap for Semiconductors ITRS), is accelerating introduction of new technologies to extend complementary MOS (CMOS) down to, and perhaps beyond, the 22-nm node This acceleration simultaneously requires the industry to intensify research on two highly challenging thrusts: one is scaling CMOS into an increasingly difficult manufacturing domain well below the 90-nm node for high performance (HP), low operating power (LOP), and low standby power (LSTP) applications, and the other is an exciting opportunity to invent fundamentally new approaches to information and signal processing to sustain functional scaling beyond the domain of CMOS This article is focused on scaling CMOS to its fundamental limits, determined by manufacturing, physics, and costs using new materials and nonclassical structures This paper provides a brief introduction to each of the new nonclassical CMOS structures This is followed by a presentation of one scenario for introduction of new structural changes to the MOSFET to scale CMOS to the end of the ITRS A brief review of electrostatic scaling of a MOSFET necessary to manage short channel effects (SCEs) at the most advanced technology nodes is also provided

369 citations

01 Jan 2005
TL;DR: In this paper, the authors proposed several new material and structural changes to the MOSFET to sustain performance increas-es of 17% per year and to manage SCEs.
Abstract: SUMMARY AND CONCLUSIONS Scaling CMOS to and beyond the 22-nm technology node(requiring a physical gate length of 9-nm or less) will probablyrequire the introduction of several new material and struc-tural changes to the MOSFET to sustain performance increas-es of 17% per year and to manage SCEs. Material changes willinclude strained silicon n- and p-channels and a new gatestack including a high-k dielectric and a metal gate electrode.Structural changes could include fully depleted UTB SOI sin-gle-gate MOSFETs, perhaps followed by fully depleted UTBdouble-gate structures. Attaining the performance require-ments for the final node for high performance applicationscould further require channels providing quasiballistic carriertransport, or very low-resistance source/drain contacts provid-ed by Schottky metal electrodes. The materials and structuralchanges actually introduced to advanced process technologieswill depend both on their readiness for manufacture and theirvalue in improving performance in the ultra-scaled devices.For example, a high-

326 citations

Journal ArticleDOI
TL;DR: Silicon on nothing (SON) as mentioned in this paper is a novel CMOS device architecture, which allows extremely thin (in the order of a few nanometers) buried dielectrics and silicon films to be fabricated with high resolution and uniformity guaranteed by epitaxial process.
Abstract: A novel CMOS device architecture called silicon on nothing (SON) is proposed, which allows extremely thin (in the order of a few nanometers) buried dielectrics and silicon films to be fabricated with high resolution and uniformity guaranteed by epitaxial process. The SON process' allows the buried dielectric (which may be an oxide but also an-air gap) to be fabricated locally in dedicated parts of the chip, which may present advantages in terms of cost and facility of system-on-chip integration. The SON stack itself is physically confined to the under-gate-plus-spacer area of a device, thus enabling extremely shallow and highly doped extensions, while leaving the HDD (highly doped drain) junctions comfortably deep. Therefore, SON embodies the ideal device architecture taking the best elements from both bulk and SOI and getting rid of their drawbacks. According to simulation results, SON enable ables excellent Ion/Ioff trade-off, suppressed self-heating, low S/D series resistance, close to ideal subthreshold slope, and high immunity to SCE and DIBL down to ultimate device dimensions of 30 to 50 nm.

262 citations

Journal ArticleDOI
TL;DR: In this article, the effects of quantum-mechanical (QM) effects on the subthreshold characteristics, including the threshold voltage, of generic undoped double-gate (DG) CMOS devices with ultrathin (Si) bodies (UTBs) are physically modeled.
Abstract: Quantum-mechanical (QM), or carrier energy-quantization, effects on the subthreshold characteristics, including the threshold voltage (V/sub t/), of generic undoped double-gate (DG) CMOS devices with ultrathin (Si) bodies (UTBs) are physically modeled. The analytic model, with dependences on the UTB thickness (t/sub Si/), the transverse electric field, and the UTB surface orientation, shows how V/sub t/ is increased, and reveals that 1) the subthreshold carrier population in higher-energy subbands is significant, 2) the QM effects in DG devices with {110}-Si surfaces, common in FinFETs, are comparable to those for {100}-Si surfaces for t/sub Si/>/spl sim/4 nm, 3) the QM effects can increase the gate swing, and (iv) the QM effects, especially for t/sub Si/

184 citations


"2-D Analytical Modeling of Surface ..." refers background in this paper

  • ...Quantum confinement effects [18] were not considered, since they become dominant for body thickness less than 5 nm....

    [...]

Journal ArticleDOI
TL;DR: In this paper, the conduction characteristics of fully depleted SOI MOSFETs studied by theoretical analysis and computer simulation are discussed, and the ideal inverse sub-threshold slope of 59.6 mV/decade is obtained if the interface-state capacitances are much smaller than the gate-oxide and silicon-film capacitance.
Abstract: The conduction characteristics of fully depleted SOI MOSFETs studied by theoretical analysis and computer simulation are discussed. In these devices the ideal inverse subthreshold slope of 59.6 mV/decade is obtained if the interface-state capacitances are much smaller than the gate-oxide and silicon-film capacitances. For above-threshold conduction, with decreasing silicon film thickness the inversion charges penetrate more deeply into the film and the transconductance increases because of the decreasing fraction of surface conduction. >

151 citations


"2-D Analytical Modeling of Surface ..." refers methods in this paper

  • ...The potential variation at both the surfaces of the silicon body can be approximated by the parabolic potential function as described in [13]...

    [...]