2-D Compact Model for Drain Current of Fully Depleted Nanoscale GeOI MOSFETs for Improved Analog Circuit Design
TL;DR: In this paper, a 2D surfacepotential-based model for the drain current of nanoscale germanium-on-insulator (GeOI) MOSFETs including the interface-trapped and fixedoxide charge densities at both front and back-gates is presented.
Abstract: Compact models for MOS devices are extremely useful as they can be incorporated in circuit simulators with sufficient accuracy. We present for the first time a 2-D surface-potential-based compact model for the drain current of nanoscale germanium-on-insulator (GeOI) MOSFETs including the interface-trapped and fixed-oxide charge densities at both front- and back-gates. The proposed drain current model is accurate, computationally efficient, and suitable for circuit simulation in the nanometer regime because no iterative loop is used anywhere. The drain current model includes velocity saturation, channel length modulation, carrier mobility degradation, and also the drain-induced barrier lowering. The model shows excellent concordance with the reported experimental transfer characteristic curves for both the high and low drain voltages and also exhibits good agreement for derivatives of drain current when compared with our TCAD simulation data for GeOI devices with channel length of 30 nm over a wide range of gate and drain bias conditions. Furthermore, our studies reveal that GeOI devices outperform silicon-on-insulator (SOI) counterparts in terms of analog figures of merit, such as transconductance, voltage gain, transconductance generation factor, and cut-off frequency, except the output conductance.
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TL;DR: In this article, a threshold voltage degradation model for gate material engineered (GME)-SB-GAA MOSFETs with the incorporation of localized charges (N it) is developed.
Abstract: The threshold voltage degradation due to the hot carrier induced localized charges (LC) is a major reliability concern for nanoscale Schottky barrier (SB) cylindrical gate all around (GAA) metal–oxide–semiconductor field-effect transistors (MOSFETs). The degradation physics of gate material engineered (GME)-SB-GAA MOSFETs due to LC is still unexplored. An explicit threshold voltage degradation model for GME-SB-GAA-MOSFETs with the incorporation of localized charges (N it) is developed. To accurately model the threshold voltage the minimum channel carrier density has been taken into account. The model renders how +/− LC affects the device subthreshold performance. One-dimensional (1D) Poisson's and 2D Laplace equations have been solved for two different regions (fresh and damaged) with two different gate metal work-functions. LCs are considered at the drain side with low gate metal work-function as N it is more vulnerable towards the drain. For the reduction of carrier mobility degradation, a lightly doped channel has been considered. The proposed model also includes the effect of barrier height lowering at the metal–semiconductor interface. The developed model results have been verified using numerical simulation data obtained by the ATLAS-3D device simulator and excellent agreement is observed between analytical and simulation results.
13 citations
TL;DR: In this paper, a 2D surface-potential-based sub-threshold model for GeSn-on-insulator (GeSnOI) MOSFETs taking into account the interface-trapped and fixed-oxide charge densities, and also quantum effects is presented.
8 citations
TL;DR: An explicit surface potential and sub-threshold current model for novel Dual Metal Gate (DMG) Asymmetric Vacuum (AV) as gate dielectric Schottky Barrier (SB) Cylindrical Gate All Around (CGAA) MOSFET with the incorporation of localized charges (Nf) is developed to provide excellent immunity against threshold voltage (Vth) degradation due to hot carriers.
6 citations
TL;DR: In this article, a new model is introduced to determine the drain current of an experimental short-channel silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) analytically.
Abstract: A new compact model is introduced to determine the drain current of an experimental short-channel silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistor (MOSFET) analytically. The effective physical parameters of the experimental nanoscale SOI MOSFET were successfully extracted for the first time using an efficient search algorithm named particle swarm optimization (PSO) as a link between the analytical drain model and the experimental data. Seven important parameters, viz. the drain-induced barrier lowering, subthreshold swing, additional resistance at the source terminal, carrier velocity, low-field carrier mobility, and threshold voltage, were sought using the PSO algorithm to obtain the best fitness value. The results revealed that the application of this PSO strategy achieved an excellent match between the proposed drain current model and experimental data notwithstanding the initial values of the fitting parameters. Also, the internal node capacitances of the short-channel SOI MOSFET were successfully extracted for use in compact models of its small-signal operation.
5 citations
01 May 2019-Microsystem Technologies-micro-and Nanosystems-information Storage and Processing Systems
TL;DR: In this article, the authors developed a low frequency noise model for symmetric double gate InAsSb channel n-MOSFETs and reported noise performance of such devices as well as amplifier circuits built using them.
Abstract: In this paper, we develop the low frequency noise (LFN) model for symmetric double gate InAsSb channel n-MOSFETs and report noise performance of such devices as well as amplifier circuits built using them. Our noise model relies on the drain current Id which is obtained from the carrier concentration and Pao-Sah’s current formulation taking into account field dependent electron mobility and interface trapped-charge density Dit. The drain current model is calibrated with reported experimental data. The calculated values of Id and transconductance gm are utilized to find power spectral density of drain current as a function of drain and gate bias voltages, channel length, channel thickness, equivalent oxide thickness and also Dit. Moreover, we have studied the performance of low noise amplifiers (LNAs) with simultaneous noise and input matching (SNIM) topology using both InAsSb and Si channel devices, and computed the minimum noise figure and output noise power density and compared the results. Our investigation reveals that InAsSb MOSFETs exhibit better low noise performance in the strong inversion region of operation at which devices are biased to operate usually for analog circuit applications. Furthermore, the LNA with InAsSb channel MOSFET exhibits noise figure of 1.38 dB in strong inversion region enabling the amplifier suitable for many applications.
3 citations
References
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Book•
IBM1
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Abstract: Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.
2,680 citations
"2-D Compact Model for Drain Current..." refers background in this paper
...Assuming drift–diffusion transport, the channel current can usually be expressed as [23]...
[...]
TL;DR: In this article, the short channel effect in fully depleted silicon-on-insulator MOSFETs has been studied by a two-dimensional analytical model and by computer simulation, and it is found that the vertical field through the depleted film strongly influences the lateral field across the source and drain regions.
Abstract: The short-channel effect in fully depleted silicon-on-insulator MOSFETs has been studied by a two-dimensional analytical model and by computer simulation. The calculated values agree well with the simulation results. It is found that the vertical field through the depleted film strongly influences the lateral field across the source and drain regions. The short-channel effect can be significantly reduced by decreasing the silicon film thickness. >
789 citations
TL;DR: In this paper, a 3D simulation study of random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFETs is presented.
Abstract: A three-dimensional (3-D) "atomistic" simulation study of random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFETs is presented. For the first time a systematic analysis of random dopant effects down to an individual dopant level was carried out in 3-D on a scale sufficient to provide quantitative statistical predictions. Efficient algorithms based on a single multigrid solution of the Poisson equation followed by the solution of a simplified current continuity equation are used in the simulations. The effects of various MOSFET design parameters, including the channel length and width, oxide thickness and channel doping, on the threshold voltage lowering and fluctuations are studied using typical samples of 200 atomistically different MOSFETs. The atomistic results for the threshold voltage fluctuations were compared with two analytical models based on dopant number fluctuations. Although the analytical models predict the general trends in the threshold voltage fluctuations, they fail to describe quantitatively the magnitude of the fluctuations. The distribution of the atomistically calculated threshold voltage and its correlation with the number of dopants in the channel of the MOSFETs was analyzed based on a sample of 2500 microscopically different devices. The detailed analysis shows that the threshold voltage fluctuations are determined not only by the fluctuation in the dopant number, but also in the dopant position.
699 citations
"2-D Compact Model for Drain Current..." refers background in this paper
...without controlling the doping level of the channel, thereby alleviating variability due to random dopant fluctuations [7]....
[...]
TL;DR: In this paper, the dual material gate (DMG) FET was proposed and demonstrated, where the gate consists of two laterally contacting materials with different work functions, such that the threshold voltage near the source is more positive than that near the drain, resulting in a more rapid acceleration of charge carriers in the channel.
Abstract: A generic new type of field effect transistor (FET), the dual material gate (DMG) FET, is proposed and demonstrated. The gate of the DMGFET consists of two laterally contacting materials with different work functions. This novel gate structure takes advantage of material work function difference in such a way that the threshold voltage near the source is more positive than that near the drain (for n-channel FET, the opposite for p-channel FET), resulting in a more rapid acceleration of charge carriers in the channel and a screening effect to suppress short-channel effects. Using the heterostructure FET as a vehicle, the principle, computer simulation results, design guidelines, processing, and characterization of the DMGFET are discussed in detail.
450 citations
TL;DR: In this paper, the authors show that blindly applying these techniques on alternative substrates can lead to incorrect conclusions, and that it is possible to both under- and overestimate the interface trap density by more than an order of magnitude.
Abstract: ldquoConventionalrdquo techniques and related capacitance-voltage characteristic interpretation were established to evaluate interface trap density on Si substrates. We show that blindly applying these techniques on alternative substrates can lead to incorrect conclusions. It is possible to both under- and overestimate the interface trap density by more than an order of magnitude. Pitfalls jeopardizing capacitance-and conductance-voltage characteristic interpretation for alternative semiconductor MOS are elaborated. We show how the conductance method, the most reliable and widely used interface trap density extraction method for Si, can be adapted and made reliable for alternative semiconductors while maintaining its simplicity.
367 citations