Journal ArticleDOI
2007 IEEE Device Research Conference: Tour de Force Multigate and Nanowire Metal Oxide Semiconductor Field-Effect Transistors and Their Application.
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Top-down fabricated gate-all-around Si nanowire FinFETs, which are compatible with the CMOS processes, offer an opportunity to circumvent limitations to boost the device scalability and performance.Abstract:
Scaling of the conventional planar complementary metal oxide semiconductor (CMOS) faces many challenges. Top-down fabricated gate-all-around Si nanowire FinFETs, which are compatible with the CMOS processes, offer an opportunity to circumvent these limitations to boost the device scalability and performance. Beyond applications in CMOS technology, the thus fabricated Si nanowire arrays can be explored as biosensors, providing a possible route to multiplexed label-free electronic chips for molecular diagnostics.read more
Citations
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Journal ArticleDOI
A Process for Topographically Selective Deposition on 3D Nanostructures by Ion Implantation
Woo-Hee Kim,Fatemeh Sadat Minaye Hashemi,Adriaan J. M. Mackus,Adriaan J. M. Mackus,Joseph A. Singh,Yeongin Kim,Dara Bobb-Semple,Yin Fan,Tobin Kaufman-Osborn,Ludovic Godet,Stacey F. Bent +10 more
TL;DR: A strategy for depositing material onto three-dimensional nanostructures with topographic selectivity using an ALD process with the aid of an ultrathin hydrophobic surface layer, demonstrating that this method can achieve selective anisotropic deposition.
Journal ArticleDOI
Area-Selective Atomic Layer Deposition Using an Inductively Coupled Plasma Polymerized Fluorocarbon Layer: A Case Study for Metal Oxides
TL;DR: In this paper, the authors demonstrate a methodology to achieve area-selective atomic layer deposition (ALD) by using inductively couple plasma (ICP) grown fluorocarbon polymer film as hydrophobic blocking layer for selective deposition.
Journal ArticleDOI
External Electric Field Modulated Electronic and Structural Properties of 〈111〉 Si Nanowires
TL;DR: In this paper, the effects of external electric field F on band gap of silicon nanowires in a diameter range of D = 0.45−1.79 nm are quantitatively calculated using density functional theory.
Journal ArticleDOI
Nanoscale selective area atomic layer deposition of TiO2 using e-beam patterned polymers
TL;DR: In this paper, an e-beam patterned growth inhibition polymer was used for patterned nano-patterning of TiO2 via area selective atomic layer deposition (AS-ALD).
Journal ArticleDOI
Atomic layer deposition of B2O3/SiO2 thin films and their application in an efficient diffusion doping process
Woo-Hee Kim,Woo-Hee Kim,Il Kwon Oh,Min Kyu Kim,Wan Joo Maeng,Chang Wan Lee,Gyeongho Lee,Clement Lansalot-Matras,Wontae Noh,David Thompson,David Chu,Hyungjun Kim +11 more
TL;DR: In this article, the authors investigated atomic layer deposition of B2O3 and SiO2 thin films using trimethylborate and bis-(diethylamino)silane (SAM-24) precursors, focusing on growth characteristics and film properties.
References
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Journal ArticleDOI
Silicon Nanowire Arrays for Label-Free Detection of DNA
Zhiqiang Gao,Ajay Agarwal,A. D. Trigg,Navab Singh,Cheng Fang,Chih-Hang Tung,Yi Fan,K.D. Buddharaju,Jin-Ming Kong +8 more
TL;DR: The SiNW array biosensor described here is ultrasensitive, non-radioactive, and more importantly, label-free, and is of particular importance to the development of gene expression profiling tools and point-of-care applications.
Proceedings ArticleDOI
Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go?
TL;DR: In this paper, Monte Carlo simulation is used to explore the characteristics of an n-channel MOSFET at the presently perceived limits of scaling, including a transconductance as high as 2300 mS/mm and an estimated ring-oscillator delay of 1.1 ps.
Proceedings ArticleDOI
Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires
Kyoung Hwan Yeo,Sung Dae Suk,Ming Li,Yun-Young Yeoh,Keun Hwi Cho,Ki-Ha Hong,Seong-Kyu Yun,Mong Sup Lee,Nammyun Cho,Kwan-Heum Lee,Duhyun Hwang,Bokkyoung Park,Dong-Won Kim,Donggun Park,Byung-Il Ryu +14 more
TL;DR: GAA TSNWFET with 15 nm gate length and 4 nm radius nanowires is demonstrated and shows excellent short channel immunity in this article, which shows high driving current of 1.94 mA/?m.
Proceedings ArticleDOI
Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance
Navab Singh,Fong Yin Lim,W. W. Fang,S. C. Rustagi,L. K. Bera,Ajay Agarwal,C.H. Tung,Keat-Mun Hoe,S. R. Omampuliyur,D. Tripathi,A. O. Adeyeye,Guo-Qiang Lo,N. Balasubramanian,Dim-Lee Kwong +13 more
TL;DR: Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K as mentioned in this paper.
Proceedings ArticleDOI
Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack
Thomas Ernst,Cecilia Dupre,C. Isheden,E. Bernard,Romain Ritzenthaler,V. Maffini-Alvaro,Jean-Charles Barbe,F. de Crecy,Alain Toffoli,C. Vizioz,S. Borel,Francois Andrieu,Vincent Delaye,D. Lafond,G. Rabille,J.M. Hartmann,Maurice Rivoire,B. Guillaumot,A. Suhm,P. Rivallin,O. Faynot,Gerard Ghibaudo,Simon Deleonibus +22 more
TL;DR: In this paper, a 3D-GAA extension of a Finfet process is proposed to achieve a 5 times higher current density per layout surface compared to planar transistors with the same gate stack (HfO 2/TiN/Poly-Si).