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Proceedings ArticleDOI

22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

TL;DR: A hierarchical BEOL with 15 levels of copper interconnect including self-aligned via processing delivers high performance with exceptional reliability in SOI CMOS 22nm technology.
Abstract: We present a fully-integrated SOI CMOS 22nm technology for a diverse array of high-performance applications including server microprocessors, memory controllers and ASICs. A pre-doped substrate enables scaling of this third generation of SOI deep-trench-based embedded DRAM for a dense high-performance memory hierarchy. Dual-Embedded stressor technology including SiGe and Si:C for improved carrier mobility in both PMOS and NMOS FETs is presented for the first time. A hierarchical BEOL with 15 levels of copper interconnect including self-aligned via processing delivers high performance with exceptional reliability.
Citations
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Journal ArticleDOI
TL;DR: This paper presents Ramulator, a fast and cycle-accurate DRAM simulator that is built from the ground up for extensibility, and is able to provide out-of-the-box support for a wide array of DRAM standards.
Abstract: Recently, both industry and academia have proposed many different roadmaps for the future of DRAM. Consequently, there is a growing need for an extensible DRAM simulator, which can be easily modified to judge the merits of today's DRAM standards as well as those of tomorrow. In this paper, we present Ramulator , a fast and cycle-accurate DRAM simulator that is built from the ground up for extensibility. Unlike existing simulators, Ramulator is based on a generalized template for modeling a DRAM system, which is only later infused with the specific details of a DRAM standard. Thanks to such a decoupled and modular design, Ramulator is able to provide out-of-the-box support for a wide array of DRAM standards: DDR3/4, LPDDR3/4, GDDR5, WIO1/2, HBM, as well as some academic proposals (SALP, AL-DRAM, TL-DRAM, RowClone, and SARP). Importantly, Ramulator does not sacrifice simulation speed to gain extensibility: according to our evaluations, Ramulator is 2.5 $\times$ faster than the next fastest simulator. Ramulator is released under the permissive BSD license.

535 citations


Additional excerpts

  • ...Performance eDRAM [28], [32]; RLDRAM3 (2011) [29]...

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Journal ArticleDOI
TL;DR: The dark memory state and present Pareto curves for compute units, accelerators, and on-chip memory, and motivates the need for HW/SW codesign for parallelism and locality are discussed.
Abstract: Unlike traditional dark silicon works that attack the computing logic, this article puts a focus on the memory part, which dissipates most of the energy for memory-bound CPU applications. This article discusses the dark memory state and present Pareto curves for compute units, accelerators, and on-chip memory, and motivates the need for HW/SW codesign for parallelism and locality. –Muhammad Shafique, Vienna University of Technology

121 citations


Cites methods from "22nm High-performance SOI technolog..."

  • ...Examples of these technological changes include increasing on-die memory using existing or emerging technologies such as eDRAM [10], STT-MRAM [11], RRAM [12], PCM [13] or 3-D Xpoint [14], to using RRAM, PCM, or Xpoint to replace DRAM or adding an additional level after DRAM in the memory hierarchy....

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Proceedings ArticleDOI
06 Mar 2014
TL;DR: The 12-core 649mm2 POWER8™ leverages IBM's 22nm eDRAM SOI technology, and microarchitectural enhancements to deliver up to 2.5× the socket performance of its 32nm predecessor, POWER7+™ [3].
Abstract: The 12-core 649mm2 POWER8™ leverages IBM's 22nm eDRAM SOI technology [1], and microarchitectural enhancements to deliver up to 2.5× the socket performance [2] of its 32nm predecessor, POWER7+™ [3]. POWER8 contains 4.2B transistors and 31.5μF of deep-trench decoupling capacitance. Three thin-oxide transistor Vts are used for power/performance tuning, and thick-oxide transistors enable high-voltage I/O and analog designs. The 15-layer BEOL contains 5-80nm, 2-144nm, 3-288nm, and 3-640nm pitch layers for low-latency communication as well as 2-2400nm ultra-thick-metal (UTM) pitch layers for low-resistance distribution of power and clocks.

81 citations


Cites methods from "22nm High-performance SOI technolog..."

  • ...The 12-core 649mm(2) POWER8TM leverages IBM’s 22nm eDRAM SOI technology [1], and microarchitectural enhancements to deliver up to 2....

    [...]

Journal ArticleDOI
TL;DR: In this article , a gate stack for high-dielectric-constant HfO2-ZrO2 superlattice heterostructures is presented, stabilized with mixed ferroelectric-antiferroelectric order, directly integrated onto Si transistors, and scaled down to approximately 20 ångströms.
Abstract: With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage1. This led to a fundamental change in the gate stack in 2008, the incorporation of high-dielectric-constant HfO2 (ref. 2), which remains the material of choice to date. Here we report HfO2-ZrO2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric-antiferroelectric order, directly integrated onto Si transistors, and scaled down to approximately 20 ångströms, the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal-oxide-semiconductor capacitors is equivalent to an effective SiO2 thickness of approximately 6.5 ångströms. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO2-based high-dielectric-constant gate stacks without scavenging the interfacial SiO2, which has adverse effects on the electron transport and gate leakage current3. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. This work demonstrates that ultrathin ferroic HfO2-ZrO2 multilayers, stabilized with competing ferroelectric-antiferroelectric order in the two-nanometre-thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond conventional HfO2-based high-dielectric-constant materials.

70 citations

Journal ArticleDOI
TL;DR: In this paper, the authors provide a review of the growth and fabrication approaches and the state-of-the-art device performance of III-V NW GAA MOSFETs, as well as an outlook of their scaling potential.
Abstract: III–V semiconductors, especially InAs, have much higher electron mobilities than Si and have been considered as promising candidates for n-channel materials for post-Si low-power CMOS logic applications. Combined with the inherent 3-D structure that enables the gate-all-around (GAA) geometry for superb gate electrostatic control, III–V nanowire (NW) MOSFETs are well positioned to extend the scaling beyond Si. This paper attempts to provide a review of the growth and fabrication approaches (both bottom–up and top–down), and the state-of-the-art device performance of III-V NW GAA MOSFETs, as well as an outlook of their scaling potential.

59 citations

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