FIG. 1. (a) Cross sectional SEM image of DNTT transistor memory device in which the thickness of PS was estimated to be 30 nm. Inset is the schematic diagram of the device structure. Different from the real device, the top Ag layer thickness is intentionally increased from 50 nm to100 nm in the sample for SEM image. (b) Transfer I-V of DNTT transistor memory device measured in the dark. (c) Schematic band diagram of transistor device working at positive gate bias and under blue light illumination, photo excited electrons in DNTT are trapped in the traps state (dotted circle) of the PS electret under positive gate bias.
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