This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication.
The final version of record is available at http://dx.doi.org/10.1109/TCSII.2020.2968246
© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any
current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new
collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other work.
1
Abstract— A low voltage linear transconductor is introduced.
The circuit is a pseudo differential architecture that operates with
±0.2V supplies and uses 900nA total biasing current. It employs a
floating battery technique to achieve low voltage operation. The
transconductor has a 1MHz bandwidth. It exhibits a SNR = 72dB,
SFDR = 42dB and THD = 0.83% for a 100mVpp 10kHz sinusoidal
input signal. Moreover, stability is not affected by the capacitance
of the signal source. The circuit has been validated with a
prototype chip fabricated in a 130nm CMOS technology.
Index Terms—Analog integrated circuits, low-power, low
voltage, linear operational transconductance amplifier.
I. INTRODUCTION
inear voltage-to-current converters (transconductors or
OTAs) and operational amplifiers (OP-AMPs) are core
circuits of analog IC design. A transconductor that is linear
over a wide differential input signal range V
d
is a key element
to implement current-mode and OTA-C systems. Some
examples of the utilization of OTAs are: wide-band amplifiers,
high frequency gm-C filters [1][2], multipliers [3] and
precision rectifiers [4], among many others.
Transconductors are used in current mode feedforward
systems with only low impedance (high frequency) and low
swing nodes in the signal path. These systems mainly rely on
current mirrors [5] and they can have very wide bandwidth.
Conventional transconductor and OP-AMP architectures use
a differential input stage. The headroom of the differential pair
HR
DP
constrains the differential and common mode input
swing to a relatively small value V
ppswing
=V
supply
-HR
DP
, where
HR
DP
~V
GS
+V
DSsat
. The headroom is directly affected by V
supply
.
With the scaling down of CMOS fabrication technologies, the
nominal supply voltage has continuously decreased. On the
other hand, the threshold voltage of PMOS and NMOS
transistors has not been reduced at the same rate. As a
comparison example a 130nm CMOS process has a nominal
This work was partially supported by Grant TEC2016-80396-C2
(AEI/FEDER). H. D. Rico-Aniles acknowledges the Mexican Consejo
Nacional de Ciencia y Tecnologia (CONACYT) for the support through an
academic scholarship with number 408946.
H. D. Rico-Aniles and J. Ramirez-Angulo are with Klipsch School of
Electrical and Computer Engineering NMSU, Las Cruces, NM, 88003
(hdrico@nmsu.edu, jairamir@nmsu.edu).
A. J. Lopez-Martin is with the Institute of Smart Cities, Public University
of Navarra, Pamplona, Spain, 31006 (antonio.lopez@unavarra.es).
R. G. Carvajal is with the Departamento de Ingenieria Electronica, Escuela
Superior de Ingenieros Universidad de Sevilla, E-41092, Spain
(carvajal@us.es).
J. Ramirez-Angulo is also affiliated with INAOE, Puebla, Mexico.
supply voltage V
supply
=1.2V and PMOS and NMOS threshold
voltages V
THN
≈ | V
THP
| ≈ 0.4V. While for a 16nm CMOS
process supply voltage has been reduced to V
supply
=0.7V while
the threshold voltage is approximately the same V
TH
≈0.4V.
This limits the portability of a circuit design with scaling
down of CMOS technologies.
Even in older technologies that can use higher supply
voltages it is convenient to operate with very low supply
voltages in order to achieve very low power dissipation which
is of paramount importance in some applications such as
biomedical [6][7] and wireless applications.
Subthreshold operation of MOS transistors is a natural
option for low voltage systems because it allows gate-source
voltages lower than V
TH
which lessen supply requirements [8]
.
Another technique that allows operation of linear
transconductors with very low supply voltages and with close
to rail to rail differential input swing is based on floating gate
transistors [9]. They use capacitive voltage dividers to reduce
swing at the input terminals of the transconductor and to shift
the DC common mode input voltage at the gates of the
differential pair close to one of the rails in order to provide
additional headroom for the input differential pair. Since they
are based on charge conservation, they cannot be used in
CMOS technologies with gate leakage. Quasi floating gate
techniques [10][11] allow implementation of dynamic low
voltage transconductors with wider differential input range.
Due to their dynamic nature and the utilization of pseudo
resistors implementing very large resistive elements they may
have large turn on times.
Another technique that allows implementation of low
voltage linear OTA’s is the bulk driven (BD) technique [12]-
[15]. In this technique input signals are injected at the bulk
terminals rather than at the gate terminals of the MOS
transistor. In order to avoid forward biasing of the bulk PN
junctions at the input terminals of the MOS transistor the
differential (and common mode) input swing is limited to
approximately ±0.3V. Larger swings result in very large input
currents that load the input signal source.
360 nW Gate-Driven Ultra-Low Voltage CMOS
Linear Transconductor with 1 MHz Bandwidth
and Wide Input Range
Hector D. Rico-Aniles, Jaime Ramirez-Angulo, Life Fellow, IEEE, Antonio J. Lopez-Martin, Senior
Member, IEEE, and Ramon G. Carvajal, Fellow, IEEE.
L
This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication.
The final version of record is available at http://dx.doi.org/10.1109/TCSII.2020.2968246
© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current
or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective
works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other work.
2
Both the floating gate technique and the bulk driven
technique suffer from significant degradation (typically a
factor 5 or higher) of input noise, input offset voltage and of
the gain-bandwidth (GB) product. In floating gate circuits this
is caused by the input capacitive divider, while, in bulk-driven
circuits it is due to the fact that the bulk transconductance gain
g
mb
is approximately a factor 5 smaller than the main
transconductance gain g
m
.
A gate-driven technique to implement low voltage OTAs is
based on CMOS inverters [16]. In this technique in order to
keep linear transconductance both inverter transistors must be
on at all times. For this reason (similar to BD circuits) the
technique of [16] has very small signal swing V
swingpp
=V
supply
-
V
GS
-V
SG
, with low supply voltage. Other limitations that affect
this technique are that the transconductance is strongly supply
and temperature dependent, it has poor CMRR and the
quiescent current (static power dissipation) is also strongly
dependent on the common mode input voltage.
In this paper we report and show experimental verification
of a gate-driven differential linear voltage-to-current converter
that operates with ±0.2V supply voltages, with large
differential and common mode input signal range and without
the GB, offset and noise degradation associated with floating
gate and bulk driven circuits. In addition, the transconductor
has high input impedance and high CMRR.
This paper is organized as follows: Section II describes the
proposed circuit. The AC and noise analysis are presented in
Sections III and 0, respectively. In Section V the simulated
and experimental results of a test chip are discussed.
Conclusions are presented in Section VI.
II. CIRCUIT DESCRIPTION
Fig. 1a shows an auxiliary circuit used to implement a wide
input range low-voltage linear V to I conversion unit. The
differential amplifier (DA) with NMOS input transistors used
in this circuit is shown in Fig. 1b. The circuit of Fig. 1a
operates as follows:
The positive input terminal of the DA is connected to a
voltage V
DDP
which is very close to V
DD
, (V
DDP
≈V
DD
-0.07V).
This provides a headroom for the DA with value HR
DP
= V
supply
- 0.07V which allows the circuit to operate with a minimum
supply voltage V
supplyMin
=HR
DP
=V
GS
+V
DSsat
. A current I
R
is
generated by connecting the voltages V
CtrlP
and voltage V
CtrlN
at the gates of transistors M
PBatt
and M
NBatt
. They generate
equal sourcing and sinking currents I
R
that flow through R and
have a value that satisfies the conditions of eq. (1) and (2),
where I
Q
=V
DDP
/R and i
s
=V
s
/R. This causes the voltage V
A
at
the negative input terminal of the DA to have a value V
DDP
equal to the voltage at the positive input terminal. Note that
the current I
s
supplied by the signal source V
S
is ideally zero.
This avoids loading the signal source V
s
by the V to I
conversion unit. Additional sinking and sourcing (eventually
scaled) replicas of the current I
R
can be generated using the
voltages V
CtrlP
and V
CtrlN
to drive PMOS and NMOS
transistors.
R
V
R
V
R
VV
I
sDDPsDDP
R
(1 )
sQR
iII
(2 )
The generation of complementary output current signals
±i
out
free from the offset term I
Q
and common mode
components requires two auxiliary V-I conversion circuits
with their input terminals connected to differential input
signals V
s1
and
V
s2
as shown in Fig. 1c. The two V-I converters
generate sinking and sourcing currents with values I
R1
=I
Q
-
V
s1
/R and I
R2
=I
Q
-V
s2
/R that are used to generate
complementary offset free output currents ±i
out
=±(V
s1
-V
s2
)/R.
The transconductor has a transconductance gain g
mOTA
=
i
out
/(V
s1
-V
s2
)=1/R.
Note that V
DDP
has a value V
DDP
=V
DD
- 0.07V to leave
headroom for the PMOS transistor M
PBatt
in Fig. 1a to operate
as a current source. The output voltage range is limited by the
drain-source saturation voltage of transistors M
PBatt,
M
NBattC
and M
NBatt
, to a value V
s
=(V
DD
-V
SS
)-2|V
DSsat
|≈ 0.26V.
(assuming V
supply
=0.4V and V
DSsat
=0.07V). On the input side
the range is also limited in the positive direction by the voltage
V
DDP
since the input signal cannot be higher than V
DDP
.
Although linear V to I conversion is achieved using the DA
with negative feedback the bandwidth of the V-I conversion
can be high since it is a local feedback loop with only parasitic
capacitances at all nodes in the circuit of Fig. 1a. If necessary,
a small compensation capacitance Cc can be used at node
V
CtrlP
of the DA to generate a dominant pole that achieves a
phase margin greater than 60
o
. A detailed analysis is presented
in the following section.
The proposed approach is based on two single ended circuits
in parallel and can be classified as a pseudo differential
scheme. In most pseudo differential systems (like an MOS
differential amplifier with its sources connected to a rail)
M
NBatt
M
NBattC
R
M
PBatt
V
CN
V
in
V
CtrlN
I
R
I
R
I
R
-
+
V
CtrlP
V
CtrlN
M
P2
M
N2
M
N2C
M
P2C
V
CN
V
CP
I
R
V
DDP
M
Pout
Out
P
Out
N
I
R
M
Nout
I
R
DA
V
A
I
S
≈ 0
a)
M
P1
'
M
P1
M
DP
M
DP
’
M
Tail
V
BN
V
in
-
V
in
+
V
Out
b)
+
V
s1
-
+
V
s2
-
i
out
i
out
Linear
V-I
V
S
Out
P
Out
N
V
DDP
Linear
V-I
V
S
Out
P
Out
N
V
DDP
V
DDP
V
DDP
c)
Fig. 1 a) Low voltage linear V-I conversion unit. b) Transistor level implementation of the differential amplifier (DA). c) Low voltage OTA with differential
input V
d
=V
s1
-V
s2
and complementary output currents using two linear V to I conversion units.
This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication.
The final version of record is available at http://dx.doi.org/10.1109/TCSII.2020.2968246
© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current
or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective
works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other work.
3
common mode and static current components are strongly
dependent on the common mode input voltage which can lead
to large and unpredictable common mode drain current values.
In pseudo differential pairs drain currents have a strong
nonlinear dependency on the input static and common mode
voltages, on transistor parameters and on temperature. In the
presence of a common mode voltage V
CM
, the common mode
current i
CM
varies following the transistor square law in strong
inversion or has an exponential dependence when the
transistors operates in subthreshold. This can cause the power
dissipation of a circuit with a pseudo differential MOS
amplifier to increase significantly with the common mode
input voltage V
CM.
This is not the case for the scheme
presented here
.
If V
s1
,V
S2
are non-complementary voltages and
have a common mode input component V
CM
=(V
s1
+V
s2
)/2, then
I
R1
and I
R2
will be given by (3) and (4). Where V
d
=V
s1
-V
s2
,
i
out
=V
d
/2R and I
CM
=(V
s1
+V
s2
)/2R. Although the proposed
architecture can be considered as a pseudo differential scheme,
it offers the advantage of having a well-defined common mode
current I
CM
. This current is linearly dependent on V
CM
and on
G=1/R. Moreover, its maximum value I
CMMAX
is reached when
V
CM
= V
SS
+V
DSsat
and is less than twice the quiescent current.
The common mode current I
CM
along with the quiescent
current I
Q
that appears in I
R1
and I
R2
are cancelled when the
current i
out
is derived.
2
))2/((
1
out
CMQ
dCMDDP
R
i
II
R
VVV
I
(3 )
2
))2/((
2
out
CMQ
dCMDDP
R
i
II
R
VVV
I
(4 )
If required, the transconductance can be made tunable by:
a) replacing R by an MOS transistor in triode region such that
the resistance can be controlled by the gate voltage of the
transistor, b) utilization of gain programmable current mirrors
in the V to I conversion unit.
III. AC ANALYSIS
A simplified AC equivalent circuit to derive the open loop
gain of the circuit of Fig. 1a is shown in Fig. 3 whose small
signal representation is shown in Fig. 2. The feedback loop is
opened, and a test voltage V
S
is applied at the gate of M
1
. The
signal source V
s
applied at node Z is represented only by its
internal impedance R
s
in parallel with C
s
. The resistance R
s
is
assumed to satisfy the condition R
s
<<r
o
. The case of a high
impedance signal source R
s
~r
o
(or higher) is not of interest
since a high impedance source performs already as a current
source and for this reason a voltage to current conversion is
not required.
M
2P
M
2
M
1
M
1P
M
Tail
M
3P
M
4
Y
M
4P
R
M
3
X
V
BN
V
Out
V
DDP
V
S
C
S
R
S
Z
Fig. 3 Simplified equivalent circuit of Fig. 1a with non-ideal signal source V
s
.
M
2
M
2
M
1
M
1
M
Tail
M
3
M
4
M
4
R
M
3
X
V
BN
V
Out
V
DDP
i
n2
2
i
n2
2
i
n1
2
i
n1
2
i
n3
2
i
n3
2
i
n4
2
i
n4
2
V
n_ineff
2
i
nR
2
Fig. 4 Circuit representation for noise analysis.
Assuming r
o
>>R, R
s
, 1/g
m
it can be shown that the open
loop gain A
OL
is approximately given by (5), having a single
pole
PX
defined by (9), where C
X
and r
X
are the capacitance
and resistance at node X, being r
X
=r
o1
||r
o2
.
The open loop DC gain (A
OLDC
)
is expressed in (6), where
A
I
(7) is the gain of the first stage and A
II
(8) is the gain of the
second stage, (V
out
/V
S
corresponds to the negative of the open
loop gain). For the second stage there is a pole-zero
cancellation.
The gain bandwidth product (GB) of the circuit is given by
(10). From this equation it can be seen that the circuit
performs approximately as a one pole system with high GB.
Therefore, the impact of the source capacitance on the stability
of the circuit can be neglected.
)/(1
PX
OLDC
OL
s
A
A
(5)
RgrgAAA
mXmIIIOLDC 31
||
(6)
XmI
rgA
1
(7)
RgA
mII 3
(8)
XX
PX
Cr
1
(9)
X
IIm
PXOLDC
C
Ag
AGB
1
(10)
C
X
r
X
g
m1
V
S
X
C
S
r
o3
g
m3
V
X
V
out
r
o4
R
S
Z
g
m3
V
X
R
Fig. 2 Small signal representation of battery and output branch.
This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication.
The final version of record is available at http://dx.doi.org/10.1109/TCSII.2020.2968246
© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current
or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective
works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other work.
4
TABLE I PERFORMANCE AND DESIGN PARAMETERS OF LOW-VOLTAGE
LINEAR TRANSCONDUCTOR
Parameter
Value
Parameter
Value
g
mOTA
(µA/V)
0.769
I
BIAS
(µA)
0.1
W
PMOS
(µm)
18
Supply Voltage (V)
±0.2
W
NMOS
(µm)
2.88
A
OL
(dB)
37.4
L
PMOS / NMOS
(nm)
360
f
-3dB
OTA(MHz)
1.099
R
(MΩ)
1.3
GB (kHz)
600
R
L
(MΩ)
1.3
Phase Margin ( ° )
52
V
DDP
(V)
0.12
Rout
(MΩ)
100
* with short circuit at output
** with open circuit at output
172
µm
153.5
µm
Fig. 5 Microphotograph of the fabricated chip with the layout.
+
-
OTA
V
out
R
L
V
S
C
D
C
D
R
bias
C
D
V
DDP_Pot
C
D
Function
Generator
Oscilloscope
Spectrum
Analyzer
V
DDP
V
DD
V
SS
V
BP
Fig. 6 Testbench diagram of the low voltage OTA with external components
and equipment.
IV. NOISE ANALYSIS
The noise representation of the circuit of Fig. 1a is shown in
Fig. 4 that includes noise current sources. The noise analysis
of this circuit, assuming A
I
>>1, leads to an equivalent input
noise voltage approximately given by (11). This expression
includes the thermal and 1/f noises. The noise bandwidth is
given by (12). In the specific case of thermal noise, it is given
by (13). If g
m1
≈g
m2
the squared RMS noise V
RMS
2
is given by
(14).
2
1
2
1
2
2
2
1
2
_
1
12
mn
n
nineffn
gi
i
iV
(11)
X
m
noise
C
g
GBBW
42
1
(12)
X
mm
noiseineffnRMS
C
kT
gg
BWVV
3
)/(12
12
2
_
2
(13)
X
RMS
C
kT
V
3
4
2
(14)
V. SIMULATION AND EXPERIMENTAL RESULTS
The proposed circuit of Fig. 1 with a single-ended output
was fabricated in a 130nm CMOS nwell process. This
technology has nominal NMOS and PMOS threshold voltages
Fig. 7 Measured output of the transconductor with 200mVpp @ 10kHz single-
ended triangular input.
Fig. 8 Experimental output waveform of the transconductor with 400mVpp @
10kHz triangular single-ended input signal.
Fig. 9 Measured spectrum with a 0.1Vpp @10kHz sinusoidal single-ended
input.
V
THN
≈ |V
THP
| ≈ 0.4V and nominal supply voltage
V
supplyTech
=|V
DD
-V
SS
|=1.2V. The circuit was designed to
operate in subthreshold with a bias current I
bias
=100nA with
dual supply voltages ±0.2V and V
DSsat
=0.07V. The bias current
leads to gate-source voltages of NMOS transistors with
aproximate values V
GSNMOS
≈0.16V and source-gate voltage of
PMOS transistors with values V
SGPMOS
≈0.14V. Fig. 5 shows a
micrograph of the fabricated circuit, while the test bench of
the circuit is shown in Fig. 6.
Table I shows the transductor design values employed. The
resistance used in the transconductor has a value R=1.3MΩ.
The associated area occupied by R was 0.00134mm
2
. The chip
also has an integrated load resistor R
L
=1.3MΩ that is
connected between the output of the transconductor and
ground. This implements a feedforward amplifier with a gain
A
V
=g
mOTA
R
L
= R
L
/R = 1V/V. An on-chip buffer with input
capacitance of approximately C
L
≈0.2pF was used at the output
of the trasconductor. The transconductor works with dual
supply voltages of ±0.2V and it was tested with a single-ended
input signal V
s1
, (V
s2
=0).
mW
MHz
P
BW
V
V
FOM
Diss
Supply
inMax
LOTA
(15 )
This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication.
The final version of record is available at http://dx.doi.org/10.1109/TCSII.2020.2968246
© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any
current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new
collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other work.
5
The measured ouput voltage of the circuit operating with
±0.2V is depicted in Fig. 7; the input signal is a 10kHz
200mVpp triangular signal. As it can be seen it has a linear
output. The ouput with a rail-rail input signal is shown in Fig.
8. This is limited by the value of voltage V
DDP
. When V
S
has a
value equal to V
DDP
the current I
R
is equal to zero (1).
The measured amplitude spectrum of the output upon
application of a 10kHz 100mVpp sinusoidal single-ended
input signal is shown in
Fig. 9. Under this conditions the transconductor with the
resistive load exhibits a SFDR= 42dB, SNR=72dB and THD =
0.83%.
The amplifier’s experimental bandwidth was 500kHz. This
bandwidth results from the internal pole of the transconductor
(approximately 1.1MHz) and the output pole of the
transconductor generated by the parallel combination of C
L
and R
L
(approximately 1 MHz). Table II shows a performance
comparison with other published linear transconductor works.
No comparison has been done to OTAs used as op-amps in
close loop since they are not linear and have a very small
differential input range. The FoM used for comparison was
proposed by [18] and expressed in (15), where V
inMax
is the
maximum input signal (for 1% THD) and V
Supply
=V
DD
-V
SS
.
PVT corners simulations have been performed to
characterize the operation of the design under different
environmental conditions. It was found that the design is
robust to PVT variations: temperature variations 0-85 °C, on
the power supply voltage variations V
DD
±10% and the process
corners: tt, ss, ff, sf and fs. The design is robust to process and
temperature variations since the circuit’s transient and AC
responses show negligible changes. Variations in the power
supply result in an ouput DC offset with maximum value of
10mV.
VI. CONCLUSION
A method to implement gate-driven ultra-low voltage linear
transconductors that are capable to operate with ±0.2V supply
voltage and wide input linear range was introduced. The
design uses 900nA total biasing current. Despite the low
biasing current and supply voltages, it achieves a relatively
high transconductor bandwidth of 1MHz. The scheme was
experimentally validated with a test chip prototype in 130nm
CMOS technology.
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TABLE II PERFORMANCE COMPARISON WITH OTHER LOW-VOLTAGE TRANSCONDUCTORS
2007 [17]
2013 [18]
2014 [19]
2019 [20]
This work
Tech. (µm)
0.5
0.18
0.13
0.18
0.13
Driven by
Gate
Gate
Bulk
Bulk
Gate
Supply (V)
±1.5
1.2
0.25
0.3
±0.2
G
M
(µS)
10
12.5
0.022
0.255
0.76
Input range (V)
0 - 3
0 - 1.10
--
0-0.3
±0.1
OTA Bandwidth (MHz)
90
14.1
--
0.000334
1.1
Noise (nV / √Hz)
1780
258.4
100(µVRMS)
1330 @10Hz
Sim
988
Sim
THD (dB) @V
PP
@ Freq (MHz)
-60 @ 6 @ 0.1
-44.2 @ 1 @ 0.1
-45.51 @ 0.1 @ --
-56.47@ 0.1 @ --
-41.61@ 0.2 @ 0.01
PSRR (dB)
35/43
47.8
--
39.9
52
Sim
CMRR(dB)
62
--
--
57
70
Sim
Power (µW)
3000
85
0.01
0.05
0.36
FoM (MHz/mW)
30
152
--
6.68
1525
Area (mm
2
)
0.1
0.0144
0.053(active)
0.035
0.0264