Proceedings ArticleDOI
3D device modeling of damage due to filamentation under an ESD event in nanometer scale drain extended NMOS (DE-NMOS)
Amitabh Chatterjee,Sameer Pendharkar,Harald Gossner,Charvaka Duvvury,Kaustav Banerjee +4 more
- pp 639-640
Reads0
Chats0
TLDR
In this paper, a detailed understanding of filamentation, through rigorous mixedmode 3D simulation in a nano-meter scale drain-extended NMOS (DE-NMOS), is presented.Abstract:
We present a detailed understanding of filamentation, through rigorous mixed-mode 3D simulation in a nano-meter scale drain-extended NMOS (DE-NMOS). Localization is first triggered in the 2D plane due to regenerative turn-on of the parasitic bipolar. 3D Simulations performed by adding width along the Z-axis (i.e., W) show a very prominent localization effect, which leads to electro-thermal runaway in the DE-NMOS and causes an irreversible damage.read more
Citations
More filters
Journal ArticleDOI
Part I: On the Behavior of STI-Type DeNMOS Device Under ESD Conditions
TL;DR: In this paper, experimental and simulation studies of shallow trench isolation (STI)-type drain-extended n-channel metaloxide-semiconductor devices under human body model (HBM)-like electrostatic discharge (ESD) conditions are given.
Proceedings Article
Source engineering for ESD robust NLDMOS
TL;DR: In this paper, an extended source diffusion width and an island shape body contact were used to improve the ESD durability and smaller die-to-die variations of NLDMOS.
Journal ArticleDOI
Off-State Degradation of High-Voltage-Tolerant nLDMOS-SCR ESD Devices
Alessio Griffoni,Shih-Hung Chen,Steven Thijs,B. Kaczer,Jacopo Franco,Dimitri Linten,A. De Keersgieter,Guido Groeseneken +7 more
TL;DR: In this paper, the off-state degradation of n-channel laterally diffused metal-oxide-semiconductor (MOS) silicon-controlled-rectifier electrostatic discharge (ESD) devices for high-voltage applications in standard lowvoltage complementary MOS technology is studied.
Proceedings ArticleDOI
On the failure mechanism and current instabilities in RESURF type DeNMOS device under ESD conditions
TL;DR: In this article, a 3D device modeling of RESURF or non-STI type DeNMOS device under ESD conditions is presented, where the impact of base push-out, pulse-to-pulse instability and electrical imbalance on the various phases of filamentation is discussed.
Proceedings ArticleDOI
Robust high current ESD performance of nano-meter scale DeNMOS by source ballasting
TL;DR: In this paper, the impact of current crowding phenomenon and role of adding a resistor across the source and ground has been broadly addressed in a macroscopically modeled and a circuit model has been established.
References
More filters
Book
ESD in silicon integrated circuits
TL;DR: ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESC in Integrated Circuits Effects of Processing and Packaging.
Journal ArticleDOI
Avalanche injection and second breakdown in transistors
P.L. Hower,V.G. Krishna Reddi +1 more
TL;DR: In this paper, it was shown that transistors having thin, lightly doped collector regions are particularly susceptible to avalanche injection, which suggests that some compromise may be necessary in the design of high-frequency power transistors.
Journal ArticleDOI
Experimental and theoretical analysis of energy capability of RESURF LDMOSFETs and its correlation with static electrical safe operating area (SOA)
TL;DR: In this paper, a new technique of distributing power within a device by applying less power at the center and more at the edges is proposed, which realizes significant improvement in energy capability by optimizing the temperature distribution within the device.