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All figures (9)
Figure 1. Schematic patterned test wafer process flow: (a) photoresist pattern on top of SiNx layer; (b) Cu nanoparticle paste distribution by
Figure 3. Process flow of wafer bonding procedure.
Figure 2. Patterened microstructrure on wafer level. (a), (b), (c) are different microstructures designed to test the Cu nanoparticle paste pattern accuracy.
Figure 8. Schematic description of particle overlapping parameters.
Figure 7. Representative porous Cu nanoparticle arrange in BCC structure. The overlapping distance between each particle was 0.2 of the particle radius.
Figure 9. Simulation results of (a) equivalent electrical resistivity, (b) equivalent electrical conductivity with different relative radius (overlapping between particles).
Figure 4. Schematic Greek cross VDP structure for sintered Cu
Figure 5. A various of Greek cross VDP structures on test wafers after Cu nanoparticle paste stencil printing.
Figure 6. Sintered Cu nanoparticle paste resistivity with different ambient atmosphere
Proceedings Article
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DOI
•
3D interconnect technology based on low temperature copper nanoparticle sintering
[...]
Baocheng Zhang
1
,
Y.C.P. Carisey
1
,
A. Damian
1
,
R. H. Poelma
1
,
Guoqi Zhang
1
,
H.W. van Zeijl
1
- Show less
+2 more
•
Institutions (1)
Delft University of Technology
1
01 Aug 2016
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