TL;DR: In this paper, a fine pitch thermal compression bonding process with coated copper nanoparticle paste was developed, which achieved better interconnect resistivity after sintering at 260 °C for 10 min, in a 700 mBar hydrogen forming gas (H 2 /N 2 ) environment.
Abstract: We explore a methodology for patterned copper nanoparticle paste for 3D interconnect applications in wafer to wafer (W2W) bonding. A novel fine pitch thermal compression bonding process (sintering) with coated copper nanoparticle paste was developed. Most of the particle size is between 10–30 nm. Lithographically defined stencil printing using photoresist and lift-off was used to apply and pattern the paste. Variations in sintering process parameters, such as: pressure, geometry and ambient atmosphere, were studied. Compared to Sn-Ag-Cu (SAC) microsolder bumps, we achieved better interconnect resistivity after sintering at 260 °C for 10 min, in a 700 mBar hydrogen forming gas (H 2 /N 2 ) environment. The electrical resistivity was 7.84 ± 1.45 µΩ·cm, which is about 4.6 times that of bulk copper. In addition, metallic nanoparticle interconnect porosity can influence the electrical properties of the interconnect. Consequently, we investigated the porosity effect on conductivity using finite element simulation. A linear relationship between the equivalent conductivity and particle overlapping ratio was found.
TL;DR: It is demonstrated that the NPC sheets can be used to achieve the Cu Cu interconnection, which is a potential bonding technology for power devices operating at high temperature.
TL;DR: In this paper , the authors developed a method to pattern nanoporous thin films with high flexibility in material selection, which enables further application on mass production of various nanoporous film-based devices in the future.
Abstract: Advances in semiconductor device manufacturing technologies are enabled by the development and application of novel materials. Especially one class of materials, nanoporous films, became building blocks for a broad range of applications, such as gas sensors and interconnects. Therefore, a versatile fabrication technology is needed to integrate these films and meet the trend towards device miniaturization and high integration density. In this study, we developed a novel method to pattern nanoporous thin films with high flexibility in material selection. Herein, Au and ZnO nanoparticles were synthesized by spark ablation and printed on a Ti/TiO2 adhesion layer, which was exposed by a lithographic stencil mask. Subsequently, the photoresist was stripped by a cost-efficient lift-off process. Nanoporous patterned features were thus obtained and the finest feature has a gap width of $0.6\ \mu \mathbf{m}$ and a line width of $2 \mu \mathbf{m}$. Using SEM and profilometers to investigate the structure of the films, it was demonstrated that the lift-off process had a minor impact on the microstructure and thickness. The samples presented a rough surface and high porosity, indicating a large surface-to-volume ratio. This is supported by the measured conductivity of Au nanoporous film, which is 12% of the value for bulk Au. As lithographic stencil printing is compatible with conventional lithographic pattering, this method enables further application on mass production of various nanoporous film-based devices in the future.
TL;DR: In this paper , the authors developed a method to pattern nanoporous thin films with high flexibility in material selection and obtained the finest feature with a gap width of ...read more
Abstract: Advances in semiconductor device manufacturing technologies are enabled by the development and application of novel materials. Especially one class of materials, nanoporous films, became building blocks for a broad range of applications, such as gas sensors and interconnects. Therefore, a versatile fabrication technology is needed to integrate these films and meet the trend towards device miniaturization and high integration density. In this study, we developed a novel method to pattern nanoporous thin films with high flexibility in material selection. Herein, Au and ZnO nanoparticles were synthesized by spark ablation and printed on a Ti/TiO 2 adhesion layer, which was exposed by a lithographic stencil mask. Subsequently, the photoresist was stripped by a cost-efficient lift-off process. Nanoporous patterned features were thus obtained and the finest feature has a gap width of $0.6\ \mu \mathbf{m}$ and a line width of $2 \mu \mathbf{m}$ . Using SEM and profilometers to investigate the structure of the films, it was demonstrated that the lift-off process had a minor impact on the microstructure and thickness. The samples presented a rough surface and high porosity, indicating a large surface-to-volume ratio. This is supported by the measured conductivity of Au nanoporous film, which is 12% of the value for bulk Au. As lithographic stencil printing is compatible with conventional lithographic pattering, this method enables further application on mass production of various nanoporous film-based devices in the future.
TL;DR: In this article , the photoresist acts as stencil mask, and a photoresists lift-off process is applied to strip the stencil stencil, which results in a chip to chip interconnect with a standard height of 20 µm.
Abstract: The continuous trend to integrate more multi-functions in a package often involves, Heterogeneous Integration of multi-functional blocks in some kind of 3D stacking. The conventional flip chip for die-on-substrate technology applies solder for integration. However, solder joint integration has the disadvantages of restricting height, reflow issues and re-melting at high operating temperatures. Nanometallic particle sintering offers a potential solution for these solder related issues. Nanometallic particle sintering occurs at low temperature and does not reflow and melt at higher temperatures. Hence, it can be applied for quite precise alignment and integration technologies, such as photonic components on silicon for harsh environment applications. In order to test this concept, we use sapphire and Si wafers with different mechanical properties, which can lead to the coefficient of thermal expansion mismatch. The sapphire chip can operate at a higher temperature applied for ultraviolet photonics application. This report describes a novel approach using copper nanoparticles paste patterned through photolithographic stencil printing. The photoresist acts as the stencil mask, and a photoresist lift-off process is applied to strip the photoresist stencil. This process has the advantages of lithographic form factor and precision and provides a chip to chip interconnect with a standard height of 20 µm.
TL;DR: This paper defines the key technologies for realizing true 3D interconnect schemes as respectively 3D-SIP,3D-WLP and 3d-SIC, which can be categorized as a more traditional packaging approach, a wafer-level-packaging, WLP approach and a foundry level ('below' passivation) approach.
Abstract: Electronic interconnection and packaging is mainly performed in a planar, 2D design style. Further miniaturization and performance enhancement of electronic systems will more and more require the use of 3D interconnection schemes. Key technologies for realizing true 3D interconnect schemes are the realization of vertical connections, either through the Si-die or through the multilayer interconnect with embedded die. Different applications require different complexities of 3D-interconnectivity. Therefore, different technologies may be used. These can be categorized as a more traditional packaging approach, a wafer-level-packaging, WLP ('above' passivation), approach and a foundry level ('below' passivation) approach. We define these technologies as respectively 3D-SIP, 3D-WLP and 3D-SIC. In this paper, these technologies are discussed in more detail.
126 citations
"3D interconnect technology based on..." refers background in this paper
...Among various of metallic nanoparticles, Cu nanoparticle paste is emerging as a promising candidate in 3D interconnect applications [11]....
TL;DR: In this article, two main challenges for wafer-to-wafer 3D integration are investigated: bonding quality (including wafer to wafer alignment) and thermal management. But, thermal effects seem to be manageable.
Abstract: In this contribution, two main challenges for wafer-to wafer 3D integration are investigated: bonding quality (including wafer-to-wafer alignment) and thermal management. The bonding process considered in this study is direct SiO2/SiO2 hydrophilic bonding. It is shown that, after process optimization, lower than 1.5 mum misalignment was achieved without significant bonding defects. In a second part, a 3D thermal modeling was done to estimate the temperature increase in a two-stratum 3D integration. Local (3D) and global (ID) modeling contribution to the maximum temperature are discussed. It is shown that, thermal resistance due to local 3D effects can be higher than ID thermal resistance. However, thermal effects seem to be manageable.
96 citations
"3D interconnect technology based on..." refers background in this paper
...Current bonding technology, including wire bonding and flip-chip technology, are facing challenges as requirements in feature size, reliability and electrical property have raised [4-10]....
TL;DR: In this article, a suspended Greek cross measurement platform is used to determine the sheet resistance of materials that would contaminate complementary metal oxide Semiconductor (CMOS) processing lines.
Abstract: This paper presents work on the development, fabrication and characterization of a suspended Greek cross measurement platform that can be used to determine the sheet resistance of materials that would contaminate Complementary Metal Oxide Semiconductor (CMOS) processing lines. The arms of the test structures are made of polysilicon/silicon nitride (Si/sub 3/N/sub 4/) to provide a carrier for the film to be evaluated and thick aluminum (Al) probe pads for multiple probing. The film to be evaluated is simply blanket deposited onto the structures and because of its design automatically forms a Greek cross structure with (Al) probe pads. To demonstrate its use, 1) gold (Au), 2) copper (Cu), and 3) silver(Ag) loaded chalcogenide glass Ag/sub y/(Ge/sub 30/Se/sub 70/)/sub 1-y/ have been blanket evaporated in various thicknesses onto the platform in the last processing step and autopatterned by the predefined shape of the Greek crosses. The suspension of the platform ensured electrical isolation between the test structure and the surrounding silicon (Si) substrate. The extracted effective resistivity for Au (5.1/spl times/10/sup -8/ /spl Omega//spl middot/m), Cu (1.8- 2.5/spl times/10/sup -8/ /spl bsol/ /spl Omega//spl middot/m) and Ag/sub y/(Ge/sub 30/Se/sub 70/)/sub 1-y/ (2.27/spl times/10/sup -5/ /spl Omega//spl middot/m-1.88 /spl Omega//spl middot/m) agree with values found in articles in the Journal of Applied Physics (1963), the Journalof Physics D: Applied Physics (1976), and the Journalof Non-Crystalline Solids (2003). These results demonstrate that the proposed Greek cross platform is fully capable to measure the sheet resistance of low (Au, Cu) and high Ag/sub y/(Ge/sub 30/Se/sub 70/)/sub 1-y/ resistive materials.
52 citations
"3D interconnect technology based on..." refers background or methods in this paper
...From Equation (1), sheet resistance can be derived by using Greek cross VDP methodology [16]....
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...Greek cross Van der Pauw (VDP) structures were designed within test wafers to measure the resistivity of Cu nanoparticle paste [16, 17]....
TL;DR: In this paper, the authors highlight some strategic research issues of sensors and actuators within the technology domain MtM, covering industrial vision, strategy and business models, and discuss some issues related to the paradigm of MtM.
Abstract: For several decades, microelectronic industries and relevant academic communities have been spending tremendous effort in developing and commercializing the Moore's law, leading to not only many breakthroughs and revolution in ICT, but also noticeable changes in the way of living of human being. While this trend is still be valid, pushing microelectronics to the nanoelectronic era, in recent years, there are ever-increasing awareness, R&D effort and business drivers to speed up the development and application of "more than Moore" that are based upon or derived from silicon technologies but do not scale with Moore's law (with typical examples as RF, power/HV, sensor/actuator/MEMS, SiP, SSL, etc.). The future business opportunities and technology challenges are the innovations and effective integration of Moore's law focusing mainly on digital function with MtM focusing mainly on non-digital function and heterogeneous integration. Starting from the rationale of MtM, this paper highlights some strategic research issues of sensors and actuators within the technology domain MtM. Some issues related to the paradigm of MtM, covering industrial vision, strategy and business models, is also discussed.
35 citations
"3D interconnect technology based on..." refers background in this paper
...Interconnect material that can be fabricated in accurate nanoscale, with advanced properties, is essential [1-3]....
TL;DR: In this paper, a numerical experimental approach for measurement of the effective Young's modulus and its size effect in homogeneous thin films and cantilevers is demonstrated, which consists in measuring the pull-in instability voltage of electro-static actuated Si nanocantilevers and bilayer Cu/Si nanocants.
Abstract: In this paper, a numerical experimental approach for measurement of the effective Young's modulus and its size effect in homogeneous thin films and cantilevers is demonstrated. Cu thin films were used as a case study. The experiment consists in measuring the pull-in instability voltage of electro-static actuated Si nanocantilevers and bilayer Cu/Si nanocantilevers. An electro-mechanical coupled finite element model of the bilayer Cu/Si nanocantilevers was used to extract the effective Young's modulus from the measured pull-in voltage. The fabricated samples consist of 340 nm thick Si cantilevers with 10 and 50 nm thick physical vapor deposited Cu films. White light interferometry was used to measure the cantilever curvature and Stoney's equation was used to calculate the thin film stress. It is shown that the pull-in instability experiment and the cantilever curvature measurement can be used for fast and easy determination of Young's modulus and film stress of 10 and 50 nm thick Cu films, respectively.
32 citations
"3D interconnect technology based on..." refers background in this paper
...Interconnect material that can be fabricated in accurate nanoscale, with advanced properties, is essential [1-3]....