4-Bit Vedic Multiplier Design Using Gate-Diffusion Input (GDI) Logic
27 Feb 2021-pp 751-762
TL;DR: In this paper, a 2-bit Urdhva cell is implemented using AND gate, XOR gate, and an inverter unlike the existing literature in which it was implemented using two half adders.
Abstract: One of the most important hardware blocks in processors is the multiplier circuit module. Area, power, and delay rule as primary factors deciding VLSI design methodologies. The work presented in this paper focuses on these three factors using Vedic multiplication approach and gate-diffusion input (GDI) logic. The ancient system of Indian mathematics being the Vedic mathematics, rediscovered from the Vedas, is more simplified, faster and accurate as compared to normal multiplication methods. The primary advantage of gate-diffusion input (GDI) logic is helping in reduced transistor count. Hence, the combination of these approaches of Vedic multiplication implemented using GDI logic results in reduced propagation delay time, lower power consumption, and less silicon area. In this paper, the proposed 2-bit Urdhva cell used is implemented using AND gate, XOR gate, and an inverter unlike the existing literature in which it is implemented using two half adders. The results are validated for the comparative advantages of our approach. The circuit simulations are carried out using UMC 90 nm technology nodes in Cadence Virtuoso.
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TL;DR: In this article, two new methods are proposed to implement the exclusive-OR and exclusive-NOR functions on the transistor level, one uses non-complementary signal inputs and the least number of transistors, while the other one improves the performance of the prior method but two more transistors are utilized.
Abstract: Two new methods are proposed to implement the exclusive-OR and exclusive-NOR functions on the transistor level. The first method uses non-complementary signal inputs and the least number of transistors. The other one improves the performance of the prior method but two more transistors are utilized. Both of them have been fully simulated by HSPICE on a SUN SPARC 2 workstation. >
355 citations
TL;DR: Gate diffusion input (GDI) - a new technique of low-power digital combinatorial circuit design - is described, showing advantages and drawbacks of GDI compared to other methods.
Abstract: Gate diffusion input (GDI) - a new technique of low-power digital combinatorial circuit design - is described. This technique allows reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Performance comparison with traditional CMOS and various pass-transistor logic design techniques is presented. The different methods are compared with respect to the layout area, number of devices, delay, and power dissipation. Issues like technology compatibility, top-down design, and precomputing synthesis are discussed, showing advantages and drawbacks of GDI compared to other methods. Several logic circuits have been implemented in various design styles. Their properties are discussed, simulation results are reported, and measurements of a test chip are presented.
299 citations
07 Aug 2002
TL;DR: Performance comparison with traditional CMOS and various PTL design techniques is presented, with respect to the layout area, number of devices, delay and power dissipation, showing advantages and drawbacks of GDI as compared to other methods.
Abstract: GDI (Gate Diffusion Input) - a new technique of low power digital circuit design is described. This technique allows reducing power consumption, delay and area of digital circuits, while maintaining low complexity of logic design. Performance comparison with traditional CMOS and various PTL design techniques is presented, with respect to the layout area, number of devices, delay and power dissipation, showing advantages and drawbacks of GDI as compared to other methods. A variety of logic gates have been implemented in 0.35 /spl mu/m technology to compare the GDI technique with CMOS and PTL. A prototype test chip of 8-bit CLA adder has been fabricated, based on GDI and CMOS cell libraries, showing up to 45% reduction in power-delay product in GDI. Properties of implemented circuits are discussed, simulation results are reported and measurements of a test chip are presented.
56 citations
TL;DR: A high speed Vedic multiplier which is efficient in terms of speed is put forward, making use of Urdhva Tiryagbhyam, a sutra from Vedic Math for multiplication and Kogge Stone algorithm for performing addition of partial products and also compares it with the characteristics of existing respective algorithms.
Abstract: is an operation much needed in Digital Signal Processing for various applications. This paper puts forward a high speed Vedic multiplier which is efficient in terms of speed, making use of Urdhva Tiryagbhyam, a sutra from Vedic Math for multiplication and Kogge Stone algorithm for performing addition of partial products and also compares it with the characteristics of existing respective algorithms. The below two algorithms aids to parallel generation of partial products and faster carry generation respectively, leading to better performance. The code is written in Verilog HDL and implemented on Xilinx Spartan 3 and Spartan 6 FPGA kit using Xilinx ISE 9.1i. The propagation delay of the implemented architecture is obtained to be 28.699ns and 15.752ns respectively.
27 citations
TL;DR: A GDI logic-based 4-bit Vedic multiplier that simplifies the multiplication process and reduces the delay; while on the other hand, GDI technique helps in minimising the transistor count (TC) and reduction in power.
Abstract: A multiplier is one of the key hardware blocks in most of the processors. Multiplication is a lengthy, time-consuming task. Vedic multiplication in field programmable gate array implementation has been proven effective in reducing the number of steps and circuit delay. Conventionally at the circuit level, complementary metal oxide semiconductor (CMOS) logic is used to design a multiplier. In CMOS circuits, the area is always an issue. Gate diffusion input (GDI)-based logic has been explored in the literature to reduce the number of transistors for various logic functions. Thus, Vedic mathematics, on the one hand, simplifies the multiplication process and reduces the delay; while on the other hand, GDI technique helps in minimising the transistor count (TC) and reduction in power. Therefore, this study puts forth a GDI logic-based 4-bit Vedic multiplier. To study the effectiveness of the GDI logic, the transient response of a 2-bit Vedic multiplier using CMOS and GDI is compared. For the 4-bit Vedic multiplier, two design approaches are taken into consideration. The performance of these circuits is analysed in terms of average power dissipation, delay, and TC. The effect of supply voltage scaling is also studied. The circuit simulations are carried out at 130 nm for bulk metal oxide semiconductor field effect transistor predictive technology model-based device parameters.
20 citations