scispace - formally typeset

Journal ArticleDOI

40-nm CMOS Wideband High-IF Receiver Using a Modified Charge-Sharing Bandpass Filter to Boost Q-Factor

26 Jan 2018-IEEE Transactions on Circuits and Systems I-regular Papers (IEEE)-Vol. 65, Iss: 8, pp 2581-2591

TL;DR: A 40-nm CMOS wideband high-IF receiver and low-noise transconductance amplifier using dual noise cancellation in order to improve its noise figure and a folded-cascode structure to increase its output impedance and prepare for a current-mode passive mixer are presented.

AbstractA 40-nm CMOS wideband high-IF receiver is presented in this paper. The low-noise transconductance amplifier (LNTA) uses dual noise cancellation in order to improve its noise figure. The LNTA has also a folded-cascode structure to increase its output impedance and prepare for a current-mode passive mixer. This structure is merged into the output stage of the LNTA, so there is no need for extra transistors. Additionally, a modified charge-sharing bandpass filter with cross-connected transconductors to boost Q-factor is proposed and discussed. The highest voltage gain achieved by the receiver (RX) is 30 dB. The RX noise figure is 3.3 dB at the maximum gain, while the IIP3 is −2.5 dBm at 1 GHz. The area of the receiver is very competitive for the wide band considered, merely 0.137 mm2. The RX and clock generation circuitry drain 25 mA from a 0.9-V supply.

Summary (3 min read)

Introduction

  • Receiver, wideband, high-IF, super-heterodyne, low noise transconductance amplifier, LNTA, switched-capacitor filter, bandpass filter, current mixer, positive feedback, Q-factor, image attenuation.
  • The low-Q filter is translated to the radio frequency (RF) input by the mixer, solving the requirement for large external filters.
  • Switched-capacitors BPFs allow for the design of fully integrated receivers with a high-IF [6], [13]–[17], avoiding the shortcomings presented previously.

II. HIGH-IF RECEIVER ARCHITECTURE

  • The receiver chain using a high-IF (HIF) architecture with quadrature down-conversion is presented in Fig.
  • Moreover, the first BPF shapes the input impedance of the mixer and attenuates the interferers.
  • In [14] the LNTA has only one stage which reduces the power consumption, but requires a cascode at the output to create a high output impedance which limits the LNTA linearity due to the 0.9 V supply voltage.
  • The SC filters operate in the discrete-time (DT) domain.
  • These replicas can reduce the blocker rejection or fold blockers on top of the main signal.

III. LNTA

  • The output impedance is one of the most important nonidealities of transconductors since it limits the AC current delivered to the load and the effective V-to-I conversion (GM).
  • The LNTA has two cascodes and one folded-cascode which ensure a high output impedance.
  • As a result, this LNTA topology completely cancels the noise of M1 and partially cancels the noise of M2, which are the major noise sources of the circuit.
  • This additional stage increases the degree of freedom of the design since it decouples the values of gm2, gm3, and Gm1.
  • In spite of any variation on the VDS of the cascode, the DC output voltage remains constant at V DD/2, which maintains these transistors in the selected operation point.

IV. FIRST FILTERING STAGE

  • The combination of a passive mixer and a chargesharing (CS) SC filter is beneficial since the mixer, if properly designed, cancels the aliasing created by the SC architecture.
  • N∗, i.e. using clock decimation for the BPF.
  • The decimation is avoided here since it would increase the noise figure due to noise folding.
  • As a result, the first BPF works at a high fs , the same as the mixer, narrowing down the topology of choice to the 1st order BPF with 4 phases (BPF 4/4) [13], which works well at high frequencies.
  • Also, the 25 %-duty-cycle non-overlapping clock drives the mixer, preventing I-Q crosstalk [18].

B. First-Order Bandpass Filter

  • The main advantage of the BPF 4/4 is its high-frequency operation; and, its main disadvantage is the low Q-factor (ideally 0.5).
  • The latter corresponds to the last value of the direct noise which remains stored across the capacitor during the OFF-phase, in which the switch is open [29].
  • Moreover, since the BPF 4/4 needs large CH capacitances to achieve a low Req , CH is differential to improve its capacitance per area.
  • The post-layout simulation results of the LNTA and first filtering stage are presented in Fig. 7a and Fig. 7b.
  • Since the input impedance of the mixer is higher at 500 MHz, the gain at this frequency is about 5 dB higher than that at the other frequencies.

V. SECOND FILTERING STAGE

  • Since the noise contribution from these cells are mitigated by LNTA gain, this filter can work at a lower sampling frequency than the previous filtering stage.
  • A second-order filter with a Q-factor higher than one can be adopted here.
  • Additionally, a cross-connection between positive and negative nodes in the direct (I) and quadrature (Q) input of the filter boosts the Q-factor with a minimum increment on power consumption and complexity of the filter.

A. GM-Cells

  • The GM-cell converts the output voltage from the previous stage to the current input required for the DT filter.
  • Moreover, since the mixer and the BPF are passive, LNTA and GM-cells are the only sources of gain in the receiver.
  • On the other hand, the 0.9 V supply headroom limits its linearity.
  • The GM-cells are based on CMOS inverters which is a topology more suited for Vdd with sub-1V constraints [30].
  • Eventually, the IIP3 can be further enhanced with thick-oxide transistors, which support a VDD up to 2.5 V; however, that design option has not been used since it would significantly increase power consumption.

B. Modified Second-Order Bandpass Filter

  • The cross-connection modification to the BPF 4/8 adopted here enhances its Q-factor, increases the image attenuation, and improves the filtering of out-of-band blockers.
  • The higher order also increases substantially the number of switches and capacitors, increasing area and power consumption.
  • Also, when β = −0.5, one of the poles is over the unit circle and the transfer function gets unstable.
  • To improve the noise figure the BPF 4/8 has to sacrifice some selectivity.
  • Thus, the circuit modification on the BPF 4/8 was used to compensate for that loss with |β| = 0.2.

VI. CLOCK GENERATION

  • The receiver requires two non-overlapping clocks: one with 25% duty-cycle, that drives the mixer and the BPF 4/4, and the other with 12.5% duty-cycle, which drives the BPF 4/8.
  • Firstly, a delay line (Fig. 11a) [32] converts the sinusoidal input signal into a rail-to-rail square wave with 50% dutycycle.
  • Then, two synchronous frequency dividers create the multiphase clock.
  • Both dividers use a chain of latches that are connected back-toback.
  • Fig. 11d shows the latches designed with tristate inverters, and Fig. 11e shows the tristate inverter topology.

VII. MEASUREMENT RESULTS

  • Most of the die area around the core is occupied by power supply decoupling capacitors.
  • Therefore, the mixer and the four phase clock generator are merged into the BPF 4/4, as shown in Fig. 12, being placed on the central region of the layout with the I path at the top and the Q path at the bottom.
  • According to their simulations and lab experiments, the mixer is the probable culprit for this gain drop.
  • Similarly, the IIP2 results are 5 dBm lower at 500 MHz and 5 dBm higher at 2 GHz than the results presented in Fig. 14c.
  • In comparison with [6] and [17] a similar IIP3 was achieved, despite the higher VDD used in these designs.

VIII. CONCLUSION

  • A 40 nm CMOS wideband receiver with small area compared to the state-of-art and good power consumption up to 4 GHz has been presented.
  • The design is based on a fully integrated inductorless LNTA using a new strategy to increase the output impedance with a folded-cascode.
  • Moreover, this paper introduced and applied in the RX a modified charge-sharing bandpass filter, which increases filter selectivity using cross-connected transconductors at the filter input.
  • This modification boosts the Q-factor without increasing the complexity or power consumption of the filter.

Did you find this useful? Give us your feedback

...read more

Content maybe subject to copyright    Report

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS 1
40-nm CMOS Wideband High-IF Receiver Using
a Modified Charge-Sharing Bandpass
Filter to Boost Q-Factor
Filipe Dias Baumgratz , Student Member, IEEE, Sandro Binsfeld Ferreira, Member, IEEE,
Michiel S. J. Steyaert, Fellow, IEEE, Sergio Bampi, Senior Member, IEEE,
and Filip Tavernier, Member, IEEE
AbstractA 40-nm CMOS wideband high-IF receiver is
presented in this paper. The low-noise transconductance ampli-
fier (LNTA) uses dual noise cancellation in order to improve its
noise figure. The LNTA has also a folded-cascode structure to
increase its output impedance and prepare for a current-mode
passive mixer. This structure is merged into the output stage of
the LNTA, so there is no need for extra transistors. Additionally,
a modified charge-sharing bandpass filter with cross-connected
transconductors to boost Q-factor is proposed and discussed. The
highest voltage gain achieved by the receiver (RX) is 30 dB. The
RX noise gure is 3.3 dB at the maximum gain, while the IIP3
is 2.5 dBm at 1 GHz. The area of the receiver is very competitive
for the wide band considered, merely 0.137 mm
2
.TheRXand
clock generation circuitry drain 25 mA from a 0.9-V supply.
Index TermsReceiver, wideband, high-IF, super-heterodyne,
low noise transconductance amplifier, LNTA, switched-capacitor
filter, bandpass filter, current mixer, positive feedback, Q-factor,
image attenuation.
I. INTRODUCTION
N
EW wireless applications such as software defined
radios or cognitive radios are demanding multi-band
and multi-standard operation, increasing the requirements for
flexibility and integrability in the radios [1]. Typical solutions
adopt either zero intermediate frequency (IF) or low-IF in the
receiver (RX) architectures since they offer less or no concerns
about image rejection. In such architectures, the channel
selection is easily performed on-chip by a low-pass filter (LPF)
after the mixer [2] which also adjusts the channel bandwidth.
Despite these interesting characteristics, the zero-IF and
low-IF topologies are constrained by 1/ f noise, second-order
Manuscript received August 4, 2017; revised November 8, 2017 and
December 19, 2017; accepted January 8, 2018. This work was supported
in part by the Brazilian National Council for Scientific and Technological
Development (CNPq), in part by CAPES, and in part by FAPERGS. This
paper was recommended by Associate Editor M. Onabajo. (Corresponding
author: Filipe Dias Baumgratz.)
F. D. Baumgratz is with PGMicro, Federal University of Rio Grande do
Sul, Porto Alegre 90040-060, Brazil, and also with KU Leuven, 3000 Leuven,
Belgium (e-mail: fdbaumgratz@inf.ufrgs.br).
S. B. Ferreira is with Unisinos University, 93020-190 S˜ao Leopoldo, Brazil.
M. S. J. Steyaert and F. Tavernier are with KU Leuven, 3000 Leuven,
Belgium.
S. Bampi is with PGMicro, Informatics Institute, Federal University of Rio
Grande do Sul, Porto Alegre 90040-060, Brazil.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2018.2792909
nonlinearity, and DC-offset. To achieve high-performance,
the receivers overcome these constraints by extensively using
calibration [3]–[5].
Super-heterodyne RX architectures are not affected by these
common issues due to their high IF [6]–[8]. Nevertheless, they
traditionally require external filters for image rejection and
channel selection. Thus, they have drawn less interest for many
years.
The N-path lter proposed in [6] is an evolution of the origi-
nal concept [9], [10], and it solves the super-heterodyne exter-
nal filter problem by implementing a bandpass filter (BPF)
using a passive switched-capacitor (SC) topology. The low-Q
filter is translated to the radio frequency (RF) input by
the mixer, solving the requirement for large external filters.
Following the introduction of this new approach, other passive
SC BPFs have been reported [11]–[16]. Those BPFs use only
switches and capacitors and are consequently more friendly
to process scaling due to the reduction of the switches ON
resistance. In fact, their performance should improve in smaller
CMOS nodes, and the scalability can be increased by using
MOS capacitors.
Switched-capacitors BPFs allow for the design of fully
integrated receivers with a high-IF [6], [13]–[17], avoiding the
shortcomings presented previously. Like the super-heterodyne
architecture, the high-IF works with IFs of tens or even
hundreds of megahertz. The image and blockers are filtered
along the receiver chain by BPFs in the RF-domain, as shown
in [6], and in the IF-domain, as shown in [6] and [13]–[16].
This paper presents a wideband high-IF receiver designed
in TSMC 40 nm CMOS, using SC BPFs to attenuate the
image and out-of-band interferers. The RX operates from
0.5 GHz to 4 GHz and two main architecture innova-
tions are introduced here. First, the low noise transconduc-
tance amplifier (LNTA) implements a clever utilization of a
folded-cascode structure, which not only increases the output
impedance of the LNTA but also reduces the number of
transistors. Second, a SC BPF, in which the Q-factor is boosted
by cross-connected transconductors at the input, is presented
and discussed. Moreover, since the mixer performs a single-
to-differential conversion, the LNTA input is single-ended and
there is no need for a chunky transformer at the input. This
results in a receiver showing high performance in a very wide
band, low power consumption, and small area.
1549-8328 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
2 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS
Fig. 1. The proposed receiver chain chain with the clock generator modules.
This paper is organized as follows. Section II discusses the
receiver architecture. The circuits that compose the receiver
are presented in sections III - VI. Section VII shows the
measurement results. Finally, section VIII summarizes the
main achievements of this paper.
II. H
IGH-IF RECEIVER ARCHITECTURE
The receiver chain using a high-IF (HIF) architecture with
quadrature down-conversion is presented in Fig. 1. This topol-
ogy has been selected due to its low-noise and high-linearity.
Despite the passive blocks such as the mixer and the BPFs,
the noise remains low thanks to the high performance LNTA.
Moreover, the first BPF shapes the input impedance of the
mixer and attenuates the interferers.
As the first block in the receiver chain, the LNTA has the
primary task of mitigating the noise contribution from the
whole receiver chain. In addition, since the following block is a
current mode mixer, the LNTA must work as a transconductor,
having a large output impedance which maximizes the AC
current delivered to the mixer [18]. The LNTA has also
an additional linearity burden; since the following mixers
and filters are passive, i.e. highly linear but gain-less and
noisy, the LNTA must have a higher gain, which reduces its
linearity. In this design the supply voltage is limited to 0.9 V,
which limits the LNTA linearity even further. Consequently,
the LNTA becomes the linearity bottleneck of the receiver.
In [6] the LNTA is a self-biased inverter-based transconduc-
tor. Also, a large on-chip transformer to convert the input from
single-ended to differential has been used, which gives an extra
10 dB of voltage gain. Recently published LNTAs [14], [17]
use noise canceling techniques to improve noise figure. In [17]
a two-stage LNTA is presented; the first stage is a high linear
low noise amplifier since it works with a supply voltage higher
than the nominal (2 V), and the second stage does the voltage
to current conversion. In [14] the LNTA has only one stage
which reduces the power consumption, but requires a cascode
at the output to create a high output impedance which limits
the LNTA linearity due to the 0.9 V supply voltage. Both
circuits create the input match using a common-gate transistor
with their sources biased with external inductors. Our proposed
circuit uses a fully integrated single-ended LNTA, without
the need for external inductors or a chunky transformer.
The choice for a single-ended topology is further discussed
in section III.
One of the most interesting features of the passive mixer
is its transparency [19]. Combining the mixer with a BPF,
the impedance seen at the input of the mixer is shaped by
the BPF transfer function (TF). Therefore, interferers that
eventually arrive at the input have lower gain than the main
signal, increasing the linearity of the LNTA and, consequently,
of the receiver. Moreover, the passive mixer creates an anti-
aliasing filter when working as a sampler [18] and it performs
the single-ended to differential conversion easily, without
requiring additional circuitry.
The SC filters operate in the discrete-time (DT) domain.
Their advantages over the continuous-time (CT) filters were
extensively discussed in [6] and [13]. Overall, DT filters, such
as the N-path lters [6], [11], [20] and the charge-sharing (CS)
filters [13]–[16], are passive filters based on SC, being more
linear and less power hungry than CT filters. Although the
N-path filter has a higher Q-factor than the CS filter, its
transfer function has several replicas, while the CS filter
transfer function has only one peak between f
s
/2and f
s
/2.
These replicas can reduce the blocker rejection or fold blockers
on top of the main signal. Hence, CS filters were chosen
for this design. Since the CS BPF has a low Q-factor [13],
the receiver needs two filter stages to attenuate the image
and the out-of-band interferers. The first filter is a first order
BPF which operates at the same sampling frequency ( f
s
)as
the mixer to properly cancel the aliasing. The second BPF,
on the other hand, does not need to use the same f
s
as the
mixer since the aliasing requirement was already met. Thus,
the clock of the second BPF is reduced, which then decimates
the input signal. In addition, the Q-factor of this BPF is
enhanced by increasing the order of the filter and by a circuit
improvement introduced in our proposed filter, as explained
ahead in section V-B.
The GM-cells shown in Fig. 1 are an intermediate stage
between the first and second filtering stages. These transcon-
ductors are needed to drive the passive second filtering stage

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
BAUMGRATZ et al.: 40-nm CMOS WIDEBAND HIGH-IF RX USING A MODIFIED CHARGE-SHARING BPF 3
Fig. 2. The proposed LNTA topology.
like the LNTA drives the passive mixer. Being the fourth
block in the chain, the GM-cells main restriction is linearity.
As depicted in the block diagram of Fig. 1, the receiver clock-
ing requires two non-overlapping clocks, two 25% duty-cycle
clocks and one 12.5% duty-cycle clock, with two different
circuits to generate them. Finally, the output buffers are simple
source-followers that isolate the circuit and provide a 50
output match to the measurement equipment.
III. LNTA
The output impedance is one of the most important non-
idealities of transconductors since it limits the AC current
delivered to the load and the effective V-to-I conversion (GM).
Therefore, the output impedance (Z
LNTA,out
)oftheLNTA
(Fig. 2) has to be higher than the input impedance of the
passive mixer (Z
MX,in
). The higher Z
LNTA,out
/Z
MX,in
ratio,
the better GM implementation.
The LNTA has two cascodes and one folded-cascode which
ensure a high output impedance. The cascodes also improve
the load isolation, so the input match and noise canceling
are immune to any load variation. The use of long channel
transistors for M2 and M3 would also increase the output
impedance without the need for cascodes, but it would harm
the input match at frequencies higher than 1 GHz since C
gs
increases proportionally to the gate length.
The folded-cascode that is created by connecting M6 to the
source of M5 is the best solution for the connection between
M6 and the output. Although M6 can be directly connected
to the output, it would reduce the output impedance.
The 50 input match is provided by M1. Since its
transconductance (g
m1
) is boosted by the local feedback
through M2, the LNTA input impedance is Z
LNTA,in
1
/g
m1
(g
m2
/g
m4
+1),whereg
m2
and g
m4
are the transconductances
of M2 and M4, respectively. However, since the intrinsic gain
(g
m
/g
ds
) for a minimum length transistor in this technology is
about 5 V/V, g
ds1
cannot be neglected, and C
gs2,3
are also not
negligible at high frequencies. The input impedance including
those effects is given by
Z
LNTA,in
=
1
g
m1
(g
m2
/g
m4
+ 1)
1 + g
ds1
R
D1
+
g
ds1
1 + g
ds1
R
D1
+ s
C
gs2
+ C
gs3
,
(1)
Thus, Z
LNTA,in
is designed to be higher than 50 to
compensate for the parasitic impedances that appear in parallel
with Z
LNTA,in
and reduce its value.
The noise canceling technique cancels only the noise of the
transistor responsible for the input matching [21]–[23], which
is M1 in this design. Hence, the noise generated by the auxil-
iary amplifier, which is initially M2 in this design, remains a
full contributor to the overall noise figure, and it needs to be
reduced by traditional means, like increasing the g
m
.
In order to further reduce noise figure, the noise of M2 is
fed back to the input and amplified through a second auxiliary
amplifier. Thus, the noise of M2 is partially canceled as
explained further. The local feedback is created by connecting
the drain of M2 to the gate of M1 [24], [25], which also
boosts the g
m
of M1. The second auxiliary amplifier is
created by using current-reuse [26], which saves power. Hence,
M3 is added to the circuit. As a result, this LNTA topology
completely cancels the noise of M1 and partially cancels the
noise of M2, which are the major noise sources of the circuit.
After the noise cancellation, M3 and R
D1
are the dominant
noise sources of the LNTA. The noise contribution of M6 is
reduced by the gain g
m1
R
D1
and can thus be neglected.
The contribution of M1 and M2 to the noise factor are
represented as follows:
F
M1
γ g
m1
R
S
g
m2
+ g
m3
g
m6
G
m1
R
D1
g
m2
+ g
m3
+ g
m6
G
m1
R
D1
2
, (2)
and
F
M2
γ g
m2
R
S
g
m1
1 + G
m1
+ G
m1
R
D1
g
m6
g
m3
g
m4
g
m2
+ g
m3
+ g
m6
G
m1
R
D1
2
.
(3)
G
m1
is g
m1
(g
m2
/g
m4
+ 1), γ is the noise coefficient, and R
s
is the signal source resistance, which is intended to be equal
to Z
LNTA,in
.
It can be deduced from (2) that the noise contribution
of M1 is zero if g
m2
+ g
m3
= g
m6
G
m1
R
D1
and from (3)
that the noise contribution of M2 is zero if 1 + G
m1
+
G
m1
R
D1
g
m6
=
g
m3
g
m4
. However, these conditions cannot be
achieved simultaneously. The best choice, therefore, is to fully
cancel the noise of M1 since it is the primary noise source and
only cancel the noise of M2 partially.
The proposed single-ended topology has two advantages
over its differential counterpart: a lower power consumption
and a larger GM while keeping the noise canceling con-
dition. The single-ended topology needs R
D1
andM6to
invert the polarity of both signal and noise. This additional
stage increases the degree of freedom of the design since
it decouples the values of g
m2
, g
m3
,andG
m1
.Inthe
differential version of this LNTA, the noise cancellation
condition would be g
m2
+ g
m3
= G
m1
since neither
M6 nor R
D1
are present. Hence, the values for g
m2
and g
m3
would be limited by G
m1
. The single-ended version, on the
other hand, does not have this limitation. Not being lim-
ited by G
m1
, g
m2
and g
m3
can be set to much higher

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
4 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS
TABLE I
LNTA S
IZING PARAMETERS
values which further reduce their noise and increase the
transconductance.
In the single-ended topology of this LNTA, the main prob-
lem is the linearity since both M6 and the cascode transistors
(M4 and M5) impose limits. The former increases the signal
distortion because M1 and R
D1
have already amplified the
signal. The latter reduces the linearity due to the four stacked
transistors within a supply voltage of 0.9 V. Furthermore,
the small V
DS
across those stacked transistors increases the
value of their distortion terms. In particular, the distortion of
M4 and M5 cannot be neglected [27].
Therefore, the gain of M6 is kept below one to minimize
distortion. The g
m
/I
D
of M1 and M2 have been selected in
such a way that their third-order distortion terms cancel each
other. The former is biased in strong inversion, and the latter in
moderate inversion [28]. Additionally, M4 and M5 are biased
like in [27] to achieve an optimal trade off between linearity
and noise.
The DC voltage at the output node is kept constant by the
DC-control block. In spite of any variation on the V
DS
of the
cascode, the DC output voltage remains constant at VDD/2,
which maintains these transistors in the selected operation
point.
Table I summarizes the sizing of the transistors, and Fig. 3
shows post-layout simulation results. The LNTA was simu-
lated using a 50 load that corresponds to the minimum
input impedance of the mixer. The simulated NF is below
2.3 dB within the entire band, and it has a minimum value
of 1.8 dB. The gain varies from 17 to 13.5 dB at 0.2 and
4 GHz respectively. Also, the input reflection coefficient (S11)
remains below 10 dB over the entire considered RF band.
Moreover, the LNTA has shown a small variation in corners
as presented in Fig. 3. The worst case NF remains below
3 dB at 125
C which is the worst case corner for noise.
Meanwhile, the voltage gain drops only 2 dB in the SS corner.
Due to parasitic capacitances, the output impedance of the
LNTA reduces at higher frequencies. Consequently, the ratio
Z
LNTA,out
/Z
MX,in
is reduced, which hampers the driving of
the mixer, and compromises the overall RX gain.
IV. F
IRST FILTERING STAGE
The combination of a passive mixer and a charge-
sharing (CS) SC filter is beneficial since the mixer, if properly
designed, cancels the aliasing created by the SC architecture.
However, the aliasing cancellation happens only if the peaks
from the BPF filter are aligned with the nulls from the mixer;
thus their f
s
have to be equal or f
BPF
s
=
f
MX
s
2n
for n N
,
i.e. using clock decimation for the BPF. The decimation is
avoided here since it would increase the noise figure due to
noise folding. As a result, the first BPF works at a high f
s
,
the same as the mixer, narrowing down the topology of choice
Fig. 3. LNTA simulation results for temperature corners 27
, 125
,and40
and process corners typical-typical (TT), fast-fast (FF), fast-slow (FS),
slow-fast (SF), and slow-slow (SS).
Fig. 4. Transfer Function of the mixer and BPF when f
s
= 4GHz.
to the 1st order BPF with 4 phases (BPF 4/4) [13], which
works well at high frequencies. Since the mixer has to match
the number of phases of the BPF, this design uses a 4-phase
passive mixer. Also, the 25 %-duty-cycle non-overlapping
clock drives the mixer, preventing I-Q crosstalk [18]. In addi-
tion, the mixer sampling frequency is four times the
LO frequency.
A. Mixer
The anti-aliasing filter is created only if the mixer, which
is presented in Fig 6, works as a sampler when its transfer
function is a sinc function [18],
H( f ) =
sin fT
s
)
π fT
s
, (4)
where T
s
is the sampling period and f the frequency in Hz.
Fig. 4 shows the TF of the anti-aliasing filter (dotted black
line). When combined with the BPF TF, the only remaining
peak is at the central frequency of the BPF while all the DT
replicas are attenuated.
A consequence of the mixer transparency is the
up-conversion of the baseband impedance, in this case an IF
impedance. Thus, its input impedance is a function not only
of the resistance of the switches, but also of the IF impedance,
which is a BPF filter in this design. According to [19],
the input impedance of a passive mixer is also affected by
the harmonics of the clock driving the switches. A resistor in
parallel with the IF impedance adds this effect to the electrical
model as can be seen in Fig. 5a. Moreover, the resistance
of only one switch has to be taken into consideration since
the switches are not closed at the same time due to the non-
overlapping clocks.

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
BAUMGRATZ et al.: 40-nm CMOS WIDEBAND HIGH-IF RX USING A MODIFIED CHARGE-SHARING BPF 5
Fig. 5. (a) The passive mixer electrical model [19]. (b) The variation of the
input impedance of the mixer with the LO frequency and (c) the value of C
R
programmed for each case. The comparison of the calculated and simulated
input impedance of the mixer at (d) 500 MHz and (e) 1 GHz.
Fig. 5a shows the electrical model proposed in [19], where
R
sw
is the resistance of the switches, R
sh
models the effect of
the clock harmonics on the input impedance, Z
IF
represents
the IF impedance, i.e. the BPF 4/4 input impedance, and ζ
is the impedance up-conversion constant. Hence, the input
impedance of the passive mixer is [19]
Z
MX,in
= R
sw
+ R
sh
||ζ Z
IF
, (5)
where ζ 0.203 and R
sh
4.3(R
LNTA,out
+ R
sw
) [19];
R
LNTA,out
is the real part of the output impedance of
the LNTA. Eq. (5) shows that Z
IF
and R
sh
have a considerable
effect on the input impedance of the mixer. Based on (5),
the input impedance of the mixer can be predicted as shown
in Fig. 5b. Since the input impedance of the BPF 4/4 decreases
with the LO frequency increase, the input impedance of the
mixer also drops, thereby reducing the overall gain. The
gain drop can be compensated by changing the value of the
capacitor C
R
(Fig. 5c) which controls the input impedance of
the BPF 4/4 and enable a flat gain response. The values pre-
dicted with (5) are reasonably accurate as observed in Fig. 5d
and Fig. 5e.
The mixer and BPF 4/4 will properly work as long as
Z
LNTA,out
Z
MX,in
, so that the Z
MX,in
is dominant.
As discussed in [18], the gain and the null depth of the
mixer are reduced if the previous condition is not fulfilled.
Henceforth, the aliasing cancellation, which is generated by
these nulls, will be limited.
There are two main reasons to reduce as much as pos-
sible Z
MX,in
: it increases the bandwidth of the LNTA, and
Z
MX,in
has to accommodate for any reduction on Z
LNTA,out
Fig. 6. Schematic of the passive mixer and the BPF 4/4.
that happens at high frequencies due to parasitic capacitances.
Otherwise, the mixer and the BPF 4/4 will not work properly at
these frequencies. Nevertheless, Z
MX,in
ends up being limited
by the CMOS technology since it is directly dependent on the
resistance of the mixer and BPF 4/4 switches.
The noise factor of the mixer and the BPF 4/4 can also be
calculated from the model in Fig. 5a and is given by
F
MX&BPF
= 1 +
v
2
n,sw
v
2
n,R
LNT A,out
+
v
2
n,sh
v
2
n,R
LNT A,out
R
LNTA,out
+ R
sw
R
sh
2
+
v
2
n,IF
v
2
n,R
LNT A,out
R
LNTA,out
+ R
sw
ζ Z
IF
2
(6)
where
v
2
n,sw
is the noise voltage of the mixer switches, v
2
n,sh
is the noise voltage of R
sh
,andv
2
n,IF
is the up-converted
noise from the IF stage, i.e. ζ
v
2
n,BPF4/4
. Eq. (6) shows
the BPF 4/4 as the main contributor to this noise factor.
Since increasing ζ Z
IF
affects the input impedance of the
mixer, the noise factor can only be effectively reduced by
reducing
v
2
n,IF
. In [19] the analysis has been done considering
the interface with a 50 antenna, which is not the case in
this design. Thus the model has to be adjusted to the LNTA
interface. For simplicity, hereafter, only the real part of the
output impedance of the LNTA will be considered.
B. First-Order Bandpass Filter
The main advantage of the BPF 4/4 is its high-frequency
operation; and, its main disadvantage is the low Q-factor
(ideally 0.5). The low Q-factor of the BPF 4/4 limits linearity
improvement on the LNTA. Fig. 6 shows the BPF 4/4, where
C
H
is the history capacitor, that stores the charge until
sampling and C
R
is the rotating capacitor, that shares the
charges with other branches.
The complex Z-domain transfer function of the
BPF 4/4 is [13]
H
4/4
(z) =
V
out
q
in
=
k
(1 αz
1
) j (1 α)z
1
, (7)

Citations
More filters


Journal ArticleDOI
11 Sep 2019
TL;DR: This work shows the opamp-based implementation of a biquadratic bandpass filter, in which Q is enhanced through performing a sensitivity analysis for each circuit element, and highlights that from sensitivity analysis one can identify the circuit elements that better enhance Q-factor.
Abstract: Active filter design is a mature topic that provides good solutions that can be implemented using discrete devices or integrated circuit technology. For instance, when the filter topologies are implemented using commercially available operational amplifiers (opamps), one can explore varying circuit parameters to tune the central frequency or enhance the quality (Q) factor. We show the addition of a feedback loop in the signal flow graph of a biquadratic filter topology, which enhances Q and highlights that a sensitivity analysis can be performed to identify which circuit elements influence central frequency, Q, or both. In this manner, we show the opamp-based implementation of a biquadratic bandpass filter, in which Q is enhanced through performing a sensitivity analysis for each circuit element. Equations for the central frequency and Q are provided to observe that there is not a direct parameter that enhances them, but we show that from sensitivity analysis one can identify the circuit elements that better enhance Q-factor.

2 citations


Proceedings ArticleDOI
01 Aug 2018
TL;DR: This paper presents a detailed design of an innovative discrete-time charge-sharing bandpass filter with a feedback technique for boosting its quality factor and the resulting selectivity of the complex filter is equivalent to a higher order filter but without the power consumption burden.
Abstract: This paper presents a detailed design of an innovative discrete-time charge-sharing bandpass filter with a feedback technique for boosting its quality factor. The design is implemented in 40-nm bulk CMOS, and it was integrated in silicon as part of a complete super-heterodyne receiver. In the proposed topology, cross-connected transconductors are used to boost the quality factor. The resulting selectivity of the complex filter is equivalent to a higher order filter but without the power consumption burden. The passive filter is fully programmable, which allows for an intermediate frequency selection in the range of 20 MHz to 100 MHz. The consequent variable bandwidth enables its use for either narrowband or wideband applications. The passive filter, with transconductance amplification and clock generation, occupies an area of $0.24 \times 0.28\ \mathbf{mm}^{2}$ with a power consumption of 8 mW when operating with a 500 MHz sampling frequency.

1 citations


Dissertation
12 Oct 2018
TL;DR: An intermediate solution to SDR receiver implementation called “Mini-SDR” architecture is proposed by exploiting the bandpass sampling concept and three CMOS radio frontends are proposed for standalone electronic attack transceiver system, dynamically reconfigurable multistandard subsampling (DRMS) radio receiver and a dual-band subsampled receiver for IEEE WLAN 802.11ac standard.
Abstract: With the evolution of wireless systems, more communication standards are being proposed while maintaining backward compatibility, therefore, there is an ever growing need for wideband multistandard receivers similar to software defined radio (SDR) receivers. For many years now, SDR or digitally reconfigurable radio research has been quite challenging with only a few reported practical prototypes with limited success. The basic demand of the SDR has been the need for a giant analog-to-digital converter (ADC) and a powerful enough digital signal processing (DSP) so that it serves as a universal radio platform receiving almost all radio standards and services. These demands are difficult to meet even in modern CMOS technologies leading to the necessity of highly flexible architectures compared to traditional receivers. To achieve this objective, digital intensive receiver architectures with passive structures are proposed. Radio frequency (RF) sampling receivers using time-interleaved (TI), RF sampling and discrete-time mixing also provide additional flexibility by employing discrete-time signal processing in analog domain. Owing to the oversampling ratio of up to 8 times in these receivers, high-performance complex frequency synthesizers are needed with stringent phase noise requirement. Moreover, the clocking schemes employed in TI RF sampling architectures result in additional timing jitter and mismatch offsets. These challenges are alleviated in a class of sampling receivers, called subsampling receivers, where the employed bandpass sampling principle results in less than the Nyquist sampling frequency. This leads to the less-complex and less power hungry frequency synthesizers. In this thesis, an intermediate solution to SDR receiver implementation called “Mini-SDR” architecture is proposed by exploiting the bandpass sampling concept. Based on the proposed Mini-SDR architecture, three CMOS radio frontends are proposed for standalone electronic attack (EA) transceiver system, dynamically reconfigurable multistandard subsampling (DRMS) radio receiver and a dual-band subsampling receiver for IEEE WLAN 802.11ac standard.

1 citations


Cites background from "40-nm CMOS Wideband High-IF Receive..."

  • ...The superhetrodyne receiver architectures [11] and homodyne receiver architecture [12] present wideband operation for multistandard receiver....

    [...]


Journal ArticleDOI
TL;DR: The proposed design achieves an unconditional stability thanks to the internal negative feedback mechanism and improves the Image Rejection Ratio (IRR) and Common Mode Rejection ratio (CMRR) of the proposed design.
Abstract: This brief presents a low-power tunable $G_{m}-C$ complex filter for wireless receiver applications. The proposed design achieves an unconditional stability thanks to the internal negative feedback mechanism. This negative feedback helps in achieving a high-frequency shift and the negative transconductance of the circuit improves the Image Rejection Ratio (IRR) and Common Mode Rejection Ratio (CMRR) of the proposed design. The proposed circuit has independent control over bandwidth and frequency shift which makes an attractive solution for multi-standard and multi-mode wireless receiver applications. A second order complex filter is designed for Long Term Evolution (LTE) application and used as a test vehicle to verify the proposed concept. The circuit is designed using a 180 nm CMOS process with a power consumption of $106~\mu \text{W}$ from a 1 V supply voltage. It is centered at 9.2 MHz with −3 dB bandwidth of 1.4 MHz and provides an IRR of 51 dB with a voltage gain of 45 dB. The total integrated in-band Input Referred Noise (IRN) is $70~\mu V_{rms}$ and FoM of 47 aJ is achieved. The area of the layout of the proposed design is $78~\mu \text{m}$ X $78~\mu \text{m}$ .

1 citations


Cites background from "40-nm CMOS Wideband High-IF Receive..."

  • ...The image frequency problem can be addressed by boosting quality factor [3]–[8]....

    [...]


References
More filters

Journal ArticleDOI
Abstract: Known elementary wide-band amplifiers suffer from a fundamental tradeoff between noise figure (NF) and source impedance matching, which limits the NF to values typically above 3 dB. Global negative feedback can be used to break this tradeoff, however, at the price of potential instability. In contrast, this paper presents a feedforward noise-canceling technique, which allows for simultaneous noise and impedance matching, while canceling the noise and distortion contributions of the matching device. This allows for designing wide-band impedance-matching amplifiers with NF well below 3 dB, without suffering from instability issues. An amplifier realized in 0.25-/spl mu/m standard CMOS shows NF values below 2.4 dB over more than one decade of bandwidth (i.e., 150-2000 MHz) and below 2 dB over more than two octaves (i.e., 250-1100 MHz). Furthermore, the total voltage gain is 13.7 dB, the -3-dB bandwidth is from 2 MHz to 1.6 GHz, the IIP2 is +12 dBm, and the IIP3 is 0 dBm. The LNA drains 14 mA from a 2.5-V supply and the die area is 0.3/spl times/0.25 mm/sup 2/.

701 citations


"40-nm CMOS Wideband High-IF Receive..." refers background in this paper

  • ...transistor responsible for the input matching [21]–[23], which is M1 in this design....

    [...]


Journal ArticleDOI
Bram Nauta1
Abstract: CMOS circuits for integrated analog filters at very high frequencies, based on transconductance-C integrators, are presented. First a differential transconductance element based on CMOS inverters is described. With this circuit a linear, tunable integrator for very-high-frequency integrated filters can be made. This integrator has good linearity properties and nondominant poles in the gigahertz range owing to the absence of internal nodes. The integrator has a tunable DC gain, resulting in a controllable integrator quality factor. Experimental results of a VHF CMOS transconductance-C low-pass filter realized in a 3- mu m CMOS process are given. Both the cutoff frequency and the quality factors can be tuned. The cutoff frequency was tuned from 22 to 98 MHz and the measured filter response is very close to the ideal response of the passive prototype filter. Furthermore, a novel circuit for automatically tuning the quality factors of integrated filters built with these transconductors is described. >

646 citations


Additional excerpts

  • ...The GM-cells are based on CMOS inverters which is a topology more suited for Vdd with sub-1V constraints [30]....

    [...]


Journal ArticleDOI
TL;DR: It is shown that a CS-stage with deep submicron transistors can have high IIP2, because the nugsldr nuds cross-term in a two-dimensional Taylor approximation of the IDS(VGS, VDS) characteristic can cancel the traditionally dominant square-law term in the IDs(V GS) relation at practical gain values.
Abstract: An inductorless low-noise amplifier (LNA) with active balun is proposed for multi-standard radio applications between 100 MHz and 6 GHz. It exploits a combination of a common-gate (CGH) stage and an admittance-scaled common-source (CS) stage with replica biasing to maximize balanced operation, while simultaneously canceling the noise and distortion of the CG-stage. In this way, a noise figure (NF) close to or below 3 dB can be achieved, while good linearity is possible when the CS-stage is carefully optimized. We show that a CS-stage with deep submicron transistors can have high IIP2, because the nugsldr nuds cross-term in a two-dimensional Taylor approximation of the IDS(VGS, VDS) characteristic can cancel the traditionally dominant square-law term in the IDS(VGS) relation at practical gain values. Using standard 65 nm transistors at 1.2 V supply voltage, we realize a balun-LNA with 15 dB gain, NF +20 dBm, while simultaneously achieving an IIP3 > 0 dBm. The best performance of the balun is achieved between 300 MHz to 3.5 GHz with gain and phase errors below 0.3 dB and plusmn2 degrees. The total power consumption is 21 mW, while the active area is only 0.01 mm2.

552 citations


Journal ArticleDOI
TL;DR: The receiver's flexible analog baseband samples the channel of interest at zero IF, and is followed by clock-programmable downsampling with embedded filtering, giving a tunable selectivity that exceeds that of an RF prefilter, and a conversion rate that is low enough for A/D conversion at only milliwatts.
Abstract: After being the subject of speculation for many years, a software-defined radio receiver concept has emerged that is suitable for mobile handsets. A key step forward is the realization that in mobile handsets, it is enough to receive one channel with any bandwidth, situated in any band. Thus, the front-end can be tuned electronically. Taking a cue from a digital front-end, the receiver's flexible analog baseband samples the channel of interest at zero IF, and is followed by clock-programmable downsampling with embedded filtering. This gives a tunable selectivity that exceeds that of an RF prefilter, and a conversion rate that is low enough for A/D conversion at only milliwatts. The front-end consists of a wideband low noise amplifier and a mixer tunable by a wideband LO. A 90-nm CMOS prototype tunes 200 kHz to 20-MHz-wide channels located anywhere from 800 MHz to 6 GHz

426 citations


"40-nm CMOS Wideband High-IF Receive..." refers methods in this paper

  • ...NEW wireless applications such as software defined radios or cognitive radios are demanding multi-band and multi-standard operation, increasing the requirements for flexibility and integrability in the radios [1]....

    [...]


Journal ArticleDOI
05 Apr 2011
TL;DR: Using a linear periodically time-variant (LPTV) model, exact expressions for the filter transfer function are derived and the behavior of the circuit including non-idealities such as maximum rejection, spectral aliasing, noise and effects due to mismatch in the paths is modeled and verified via measurements.
Abstract: A differential single-port switched-RC N-path filter with band-pass characteristic is proposed. The switching frequency defines the center frequency, while the RC-time and duty cycle of the clock define the bandwidth. This allows for high-Q highly tunable filters which can for instance be useful for cognitive radio. Using a linear periodically time-variant (LPTV) model, exact expressions for the filter transfer function are derived. The behavior of the circuit including non-idealities such as maximum rejection, spectral aliasing, noise and effects due to mismatch in the paths is modeled and verified via measurements. A simple RLC equivalent circuit is provided, modeling bandwidth, quality factor and insertion loss of the filter. A 4-path architecture is realized in 65 nm CMOS. An off-chip transformer acts as a balun, improves filter-Q and realizes impedance matching. The differential architecture reduces clock-leakage and suppresses selectivity around even harmonics of the clock. The filter has a constant -3 dB bandwidth of 35 MHz and can be tuned from 100 MHz up to 1 GHz. Over the whole band, IIP3 is better than 14 dBm, P1dB=2 dBm and the noise figure is 3-5 dB, while the power dissipation increases from 2 mW to 16 mW (only clocking power).

341 citations


"40-nm CMOS Wideband High-IF Receive..." refers background in this paper

  • ...Overall, DT filters, such as the N-path filters [6], [11], [20] and the charge-sharing (CS) filters [13]–[16], are passive filters based on SC, being more linear and less power hungry than CT filters....

    [...]


Frequently Asked Questions (1)
Q1. What are the contributions mentioned in the paper "40-nm cmos wideband high-if receiver using a modified charge-sharing bandpass filter to boost q-factor" ?

A 40-nm CMOS wideband high-IF receiver is presented in this paper.