40-nm CMOS Wideband High-IF Receiver Using a Modified Charge-Sharing Bandpass Filter to Boost Q-Factor
Summary (3 min read)
- Receiver, wideband, high-IF, super-heterodyne, low noise transconductance amplifier, LNTA, switched-capacitor filter, bandpass filter, current mixer, positive feedback, Q-factor, image attenuation.
- The low-Q filter is translated to the radio frequency (RF) input by the mixer, solving the requirement for large external filters.
- Switched-capacitors BPFs allow for the design of fully integrated receivers with a high-IF , –, avoiding the shortcomings presented previously.
II. HIGH-IF RECEIVER ARCHITECTURE
- The receiver chain using a high-IF (HIF) architecture with quadrature down-conversion is presented in Fig.
- Moreover, the first BPF shapes the input impedance of the mixer and attenuates the interferers.
- In  the LNTA has only one stage which reduces the power consumption, but requires a cascode at the output to create a high output impedance which limits the LNTA linearity due to the 0.9 V supply voltage.
- The SC filters operate in the discrete-time (DT) domain.
- These replicas can reduce the blocker rejection or fold blockers on top of the main signal.
- The output impedance is one of the most important nonidealities of transconductors since it limits the AC current delivered to the load and the effective V-to-I conversion (GM).
- The LNTA has two cascodes and one folded-cascode which ensure a high output impedance.
- As a result, this LNTA topology completely cancels the noise of M1 and partially cancels the noise of M2, which are the major noise sources of the circuit.
- This additional stage increases the degree of freedom of the design since it decouples the values of gm2, gm3, and Gm1.
- In spite of any variation on the VDS of the cascode, the DC output voltage remains constant at V DD/2, which maintains these transistors in the selected operation point.
IV. FIRST FILTERING STAGE
- The combination of a passive mixer and a chargesharing (CS) SC filter is beneficial since the mixer, if properly designed, cancels the aliasing created by the SC architecture.
- N∗, i.e. using clock decimation for the BPF.
- The decimation is avoided here since it would increase the noise figure due to noise folding.
- As a result, the first BPF works at a high fs , the same as the mixer, narrowing down the topology of choice to the 1st order BPF with 4 phases (BPF 4/4) , which works well at high frequencies.
- Also, the 25 %-duty-cycle non-overlapping clock drives the mixer, preventing I-Q crosstalk .
B. First-Order Bandpass Filter
- The main advantage of the BPF 4/4 is its high-frequency operation; and, its main disadvantage is the low Q-factor (ideally 0.5).
- The latter corresponds to the last value of the direct noise which remains stored across the capacitor during the OFF-phase, in which the switch is open .
- Moreover, since the BPF 4/4 needs large CH capacitances to achieve a low Req , CH is differential to improve its capacitance per area.
- The post-layout simulation results of the LNTA and first filtering stage are presented in Fig. 7a and Fig. 7b.
- Since the input impedance of the mixer is higher at 500 MHz, the gain at this frequency is about 5 dB higher than that at the other frequencies.
V. SECOND FILTERING STAGE
- Since the noise contribution from these cells are mitigated by LNTA gain, this filter can work at a lower sampling frequency than the previous filtering stage.
- A second-order filter with a Q-factor higher than one can be adopted here.
- Additionally, a cross-connection between positive and negative nodes in the direct (I) and quadrature (Q) input of the filter boosts the Q-factor with a minimum increment on power consumption and complexity of the filter.
- The GM-cell converts the output voltage from the previous stage to the current input required for the DT filter.
- Moreover, since the mixer and the BPF are passive, LNTA and GM-cells are the only sources of gain in the receiver.
- On the other hand, the 0.9 V supply headroom limits its linearity.
- The GM-cells are based on CMOS inverters which is a topology more suited for Vdd with sub-1V constraints .
- Eventually, the IIP3 can be further enhanced with thick-oxide transistors, which support a VDD up to 2.5 V; however, that design option has not been used since it would significantly increase power consumption.
B. Modified Second-Order Bandpass Filter
- The cross-connection modification to the BPF 4/8 adopted here enhances its Q-factor, increases the image attenuation, and improves the filtering of out-of-band blockers.
- The higher order also increases substantially the number of switches and capacitors, increasing area and power consumption.
- Also, when β = −0.5, one of the poles is over the unit circle and the transfer function gets unstable.
- To improve the noise figure the BPF 4/8 has to sacrifice some selectivity.
- Thus, the circuit modification on the BPF 4/8 was used to compensate for that loss with |β| = 0.2.
VI. CLOCK GENERATION
- The receiver requires two non-overlapping clocks: one with 25% duty-cycle, that drives the mixer and the BPF 4/4, and the other with 12.5% duty-cycle, which drives the BPF 4/8.
- Firstly, a delay line (Fig. 11a)  converts the sinusoidal input signal into a rail-to-rail square wave with 50% dutycycle.
- Then, two synchronous frequency dividers create the multiphase clock.
- Both dividers use a chain of latches that are connected back-toback.
- Fig. 11d shows the latches designed with tristate inverters, and Fig. 11e shows the tristate inverter topology.
VII. MEASUREMENT RESULTS
- Most of the die area around the core is occupied by power supply decoupling capacitors.
- Therefore, the mixer and the four phase clock generator are merged into the BPF 4/4, as shown in Fig. 12, being placed on the central region of the layout with the I path at the top and the Q path at the bottom.
- According to their simulations and lab experiments, the mixer is the probable culprit for this gain drop.
- Similarly, the IIP2 results are 5 dBm lower at 500 MHz and 5 dBm higher at 2 GHz than the results presented in Fig. 14c.
- In comparison with  and  a similar IIP3 was achieved, despite the higher VDD used in these designs.
- A 40 nm CMOS wideband receiver with small area compared to the state-of-art and good power consumption up to 4 GHz has been presented.
- The design is based on a fully integrated inductorless LNTA using a new strategy to increase the output impedance with a folded-cascode.
- Moreover, this paper introduced and applied in the RX a modified charge-sharing bandpass filter, which increases filter selectivity using cross-connected transconductors at the filter input.
- This modification boosts the Q-factor without increasing the complexity or power consumption of the filter.
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A 40-nm CMOS wideband high-IF receiver is presented in this paper.