5.10 A 1A LDO regulator driven by a 0.0013mm 2 Class-D controller
01 Feb 2017-pp 104-105
TL;DR: A Class-D driven LDO with a distributed-gate-resistance power transistor is proposed to achieve low quiescent current, low output ripple and small silicon area at the same time.
Abstract: A low-dropout (LDO) regulator generates a DC supply for electronic systems. Today's high-throughput wireless system-on-chips (SOCs) require large dynamic range of supply current, which demands a high current capacity LDO. The power transistor of the LDO scales up with the maximum load current. A conventional analog LDO consumes high quiescent current to drive the large power transistor for loop stability [2]. For a digital LDO, the control circuits increase with the size of the power transistor, which results in more area overhead and design complexity [4]. A Class-D driven LDO with a distributed-gate-resistance power transistor is proposed to achieve low quiescent current, low output ripple and small silicon area at the same time. This paper presents a 1.8V-to-1.2V input, 1.05V-output LDO with 1A load capacity.
Citations
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Proceedings Article•
01 Jan 2005
TL;DR: In this paper, the authors demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology, which enables a 90 mVp-p output droop for a 100mA load step with only a small on-chip decoupling capacitor of 0.6 nF.
Abstract: We demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast single-stage load regulation achieves a 0.54-ns response time at 94% current efficiency. For a 1.2-V input voltage and 0.9-V output voltage the regulator enables a 90 mVp-p output droop for a 100-mA load step with only a small on-chip decoupling capacitor of 0.6 nF. By using a PMOS pull-up transistor in the output stage we achieved a small regulator area of 0.008 mm 2 and a minimum dropout voltage of 0.2 V for 100 mA of output current. The area for the 0.6-nF MOS capacitor is 0.090 mm 2 .
24 citations
TL;DR: This brief proposes a fully integrated output capacitor-less low-dropout regulator (LDO) using a voltage difference to time converter (VDTC) that allows low voltage operation and significantly reduces the quiescent current.
Abstract: This brief proposes a fully integrated output capacitor-less low-dropout regulator (LDO) using a voltage difference to time converter (VDTC). Proposed dynamic amplifier based VDTC allows low voltage operation and significantly reduces the quiescent current. The linear characteristics of VDTC result in output ripple-less operation and good regulation performance. Using direct output feedback through a small coupling capacitor, the gate voltage of the power transistor is instantly compensated to mitigate fluctuation of the output voltage when a sharp load transient occurs. Fabricated in 65 nm LP CMOS, the proposed LDO demonstrates a wide operation range with an input voltage range of 0.6–1.2 V and a load current of over 30 mA across all voltages without an output capacitor. With reduced output impedance due to direct output feedback, the measured undershoot is 158 mV, which is recovered in $9.6~{\mu }\text{s}$ , when the load current changes by 28 mA in 1 ns. The peak current efficiency is more than 99.99% and the figure of merit (FOM) is 0.202 fs. The active area of the control block is 0.002 mm2.
10 citations
Cites background from "5.10 A 1A LDO regulator driven by a..."
...Recently, a Class-D LDO [11] was proposed to combine the benefits of both analog and digital LDOs, avoiding high bias current and high clock frequency....
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DOI•
01 Jan 2021TL;DR: In this article, an analog-assisted digital LDO with a single, large output pMOS biased in sub-threshold to enable fast response to output voltage droop is described.
Abstract: This letter describes an analog-assisted digital LDO that cascades a conventional digital LDO structure with a single, large output pMOS biased in subthreshold to enable fast response to output voltage droop. By digitally controlling the gate voltage of the output pMOS, the operating regime of the output transistor is decoupled from the input voltage. In addition, a 2-pF capacitor between the output voltage and the gate of the output pMOS creates a high-pass path to boost the output current when voltage droops occur. The proposed design is fabricated in 28-nm CMOS, and it enables a uniform transient response over an input voltage range of 0.5-0.9 V. The measured voltage droop when load current changes from 10 to 60 mA (1-ns edge time) is 110 mV at input voltages of both 0.5 and 0.9 V, resulting in a speed FOM of 1.44 fs.
4 citations
18 Jun 2023
TL;DR: In this article , a fast-transient mitigation technique was proposed for a self-timed, dual-loop Asynchronous Digital LDO, which relies on a simple Request-Acknowledge (REQ-ACK) protocol to manage the power stage.
Abstract: In this paper is presented a fast-transient mitigation technique which applies to a self-timed, dual-loop Asynchronous Digital LDO. The number of conducting transistors is controlled by an Asynchronous Finite State Machine (AFSM) employing a linear-search algorithm that is able to operate without a clock oscillator. It relies on a simple Request-Acknowledge (REQ-ACK) protocol to manage the power stage. The proposed mitigation technique has two components. One relies on using a secondary loop that has bigger transistors. The LDO reaches steady state faster than the main loop due to the higher adjustment steps. The other component controls the operating frequency by altering the REQ-ACK protocol in order to sample and update the output faster. The circuit was simulated and fabricated using Infineon’s proprietary 130nm BCD technology and was assembled in SSOP-14 plastic package. Also, the proposed circuit was measured and the results show more than 50 percent improvement and a settle time reduction with a factor of 4 on sudden load changes while a light increase in output voltage ripple for steady-state operation must be considered.
18 Jun 2023
TL;DR: In this article , a fast-transient mitigation technique was proposed for a self-timed, dual-loop Asynchronous Digital LDO, which relies on a simple Request-Acknowledge (REQ-ACK) protocol to manage the power stage.
Abstract: In this paper is presented a fast-transient mitigation technique which applies to a self-timed, dual-loop Asynchronous Digital LDO. The number of conducting transistors is controlled by an Asynchronous Finite State Machine (AFSM) employing a linear-search algorithm that is able to operate without a clock oscillator. It relies on a simple Request-Acknowledge (REQ-ACK) protocol to manage the power stage. The proposed mitigation technique has two components. One relies on using a secondary loop that has bigger transistors. The LDO reaches steady state faster than the main loop due to the higher adjustment steps. The other component controls the operating frequency by altering the REQ-ACK protocol in order to sample and update the output faster. The circuit was simulated and fabricated using Infineon’s proprietary 130nm BCD technology and was assembled in SSOP-14 plastic package. Also, the proposed circuit was measured and the results show more than 50 percent improvement and a settle time reduction with a factor of 4 on sudden load changes while a light increase in output voltage ripple for steady-state operation must be considered.
References
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TL;DR: In this article, the authors demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology, which enables a 90 mV/sub P-P/output droop with only a small on-chip decoupling capacitor of 0.6 nF.
Abstract: We demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast single-stage load regulation achieves a 0.54-ns response time at 94% current efficiency. For a 1.2-V input voltage and 0.9-V output voltage the regulator enables a 90 mV/sub P-P/ output droop for a 100-mA load step with only a small on-chip decoupling capacitor of 0.6 nF. By using a PMOS pull-up transistor in the output stage we achieved a small regulator area of 0.008 mm/sup 2/ and a minimum dropout voltage of 0.2 V for 100 mA of output current. The area for the 0.6-nF MOS capacitor is 0.090 mm/sup 2/.
509 citations
TL;DR: In this article, the impact of gate resistance on cut-off frequency, maximum frequency of oscillation (f/sub max/), thermal noise, and time response of wide MOS devices with deep submicron channel lengths was analyzed.
Abstract: This paper describes the impact of gate resistance on cut-off frequency (f/sub T/), maximum frequency of oscillation (f/sub max/), thermal noise, and time response of wide MOS devices with deep submicron channel lengths. The value of f/sub T/ is proven to be independent of gate resistance even for distributed structures. An exact relation for f/sub max/ is derived and it is shown that, to predict f/sub max/, thermal noise, and time response, the distributed gate resistance can be divided by a factor of 3 and lumped into a single resistor in series with the gate terminal. >
230 citations
"5.10 A 1A LDO regulator driven by a..." refers background in this paper
...The whole power transistor array can be seen as a distributed RC network, whose transfer function has been derived in [6]....
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01 Feb 2008
TL;DR: A low-voltage fast transient-response LDO regulator using an inexpensive 0.35 mum CMOS process is presented in this paper, which features a current-efficient adaptively biased regulation scheme using a low- voltage high-speed super current mirror and does not require a compensation capacitor.
Abstract: Portable applications often need multiple voltages controlled by a power management IC to power up many functional blocks A switching pre-regulator is usually followed by a low dropout (LDO) regulator to provide a regulated power source for noise-sensitive blocks The LDO regulator has to be stable for all load conditions and frequency compensation is usually needed to stabilize the regulation loop The output voltage droop due to rapid and large load changes could be minimized with a fast regulation loop, such that functional blocks powered by the same LDO regulator would have low crosstalk noise A low-voltage fast transient-response LDO regulator using an inexpensive 035 mum CMOS process is presented in this paper It features a current-efficient adaptively biased regulation scheme using a low-voltage high-speed super current mirror and does not require a compensation capacitor It is stabilized by a low-cost low-ESR ceramic filter capacitor of 1 muF The adaptively biased error amplifier EA drives a small transconductance cell to modulate the output current through a transient-enhanced super current-mirror (SCM)
159 citations
"5.10 A 1A LDO regulator driven by a..." refers background in this paper
...A conventional analog LDO consumes high quiescent current to drive the large power transistor for loop stability [2]....
[...]
06 Mar 2014
TL;DR: On-chip LDOs with PSR in the GHz range are in high demand for wideband optical communication systems because there is only one photo detector in the optical receiver and supply voltage variations would degrade its sensitivity severely.
Abstract: High performance low-dropout regulators (LDOs) are indispensable in a systemon-a-chip (SoC) due to their low output noise, fast transient response and good power supply rejection (PSR) characteristics. In general, differential analog circuit loads need an LDO with high PSR, digital circuit loads need an LDO with fast load transient response, while single-ended analog/RF circuit loads need an LDO with both high PSR and fast transient response. Figure 17.11.1 shows an LDO embedded in an optical receiver that helps improve the sensitivity of the front-end system. On-chip LDOs with PSR in the GHz range are in high demand for wideband optical communication systems because there is only one photo detector in the optical receiver and supply voltage variations would degrade its sensitivity severely.
99 citations
25 Feb 2016
TL;DR: To reduce the number of external capacitors, one power voltage level from the PMIC is converted into a variety of power voltage levels inside the mobile AP and simplifies PCB routes, integrated low-dropout regulators (LDOs) are preferred in mobile APs.
Abstract: A modern mobile application processor (AP) requires a variety of power voltage levels, which increases the number of external capacitors around the mobile AP. This is because the supply PCB routes from the power management IC (PMIC) to the AP have parasitic inductors. The parasitic inductors introduce ripples on power voltage lines. Therefore, external capacitors are required on the PCB routes between the PMIC and the mobile AP. To reduce the number of external capacitors, one power voltage level from the PMIC is converted into a variety of power voltage levels inside the mobile AP. This both reduces external capacitors as well as the number of power pins on the mobile AP and simplifies PCB routes. For such reasons, integrated low-dropout regulators (LDOs) are preferred in mobile APs.
25 citations
"5.10 A 1A LDO regulator driven by a..." refers background in this paper
...For a digital LDO, the control circuits increase with the size of the power transistor, which results in more area overhead and design complexity [4]....
[...]