80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity
15 Jun 2016-pp 1-2
TL;DR: An 80Kb logic Embedded Multi-Time Programmable Memory (MTPM) employs charge trapping and de-trapping behavior in 32nm/22nm High-K transistor, resulting in no added process complexity.
Abstract: An 80Kb logic Embedded Multi-Time Programmable Memory (MTPM) employs charge trapping and de-trapping behavior in 32nm/22nm High-K transistor, resulting in no added process complexity. Multi-step verification with overwrite protection employs block-write and signal margin degradation (∼30%) to satisfy 10 year retention at 105° C.
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TL;DR: In this paper, total ionizing-dose (TID) effects for 22-nm fully-depleted silicon-on-insulator (FDSOI) and 14-nm bulk FinFET charge-trap memory transistors were investigated.
Abstract: Total-ionizing-dose (TID) effects are investigated for 22-nm fully-depleted silicon-on-insulator (FDSOI) and 14-nm bulk FinFET charge-trap memory transistors. Electron trapping in the gate dielectric establishes the programmed memory state for both silicon on insulator (SOI) and bulk devices. To first order, ionizing radiation does not interact strongly with programing-induced charges in the gate dielectric for either device type. Hole trapping in the buried oxide dominates the TID response of the 22-nm FDSOI devices. The 14-nm bulk devices with two fins and total effective fin widths of 150 nm are minimally affected by TID, but the subthreshold leakage of devices with 40 fins and total effective fin widths of $3~\mu \text{m}$ increases with increasing TID. When devices are programmed or reprogrammed after irradiation, significant increases in subthreshold slope are observed due to the generation of interface traps, border traps, and/or charge lateral nonuniformities.
12 citations
Cites methods from "80Kb 10ns read cycle logic Embedded..."
...this study share similar memory transistor properties with the 22-nm FDSOI-based devices [7], [12]–[15]....
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TL;DR: A fully CMOS-compatible multi-level non-volatile memory technology, especially suitable for storing the weights of artificial neural networks on chip with low cost, high density, and high power-efficiency is presented.
Abstract: We present a fully CMOS-compatible multi-level non-volatile memory technology, without any special process cost. It is especially suitable for storing the weights of artificial neural networks on chip with low cost, high density, and high power-efficiency. We use hot carrier injection to program the single-transistor cells, and we conduct charge pumping experiments which identify interfacial traps, rather than bulk oxide traps, as the dominant factor in producing stable $I-V$ shifts. We also derive a new physics-based experimentally verified logarithmic model to explain the rate of interfacial trap generation in large $I-V$ shift regimes where the conventional power-law no longer applies. We fabricate two chips, one using TSMC’s 16 nm FinFET and the other in 28 nm planar, and show the FinFET cells are more favorable for non-volatile memory due to their better channel control. We store multiple levels in each FinFET cell using a “program and check” strategy which sets memory cells’ currents with standard deviations less than $2~{\mu }A$ across a shifting range of over $100~{\mu }A$ . We demonstrate 8 level FinFET cells with extrapolated 10-year charge loss within 10% at 125 °C.
8 citations
01 Mar 2018
TL;DR: The NoIF enables integration of ultra large scale heterogeneous systems within the technologically mature Si-IF platform and is based on utility dies which serve as intelligent nodes within the network.
Abstract: Silicon interconnect fabric (Si-IF) supports integration of bare dies using thermal compression bonding on a Si wafer substrate. Fine pitch (2 to 10 μm) horizontal and vertical inter-connects are feasible within the Si-IF using standard Si processing techniques. A network on interconnect fabric (NoIF) is proposed in this paper. The NoIF enables integration of ultra large scale heterogeneous systems within the technologically mature Si-IF platform. NoIF is based on utility dies which serve as intelligent nodes within the network. NoIF enables global communication, power conversion and management, synchronization, processing and memory capabilities, redundancy allocation, and test of the Si-IF, and the utility and functional dies.
7 citations
Cites background from "80Kb 10ns read cycle logic Embedded..."
...At the system level, The UDs can store information regarding the functionality of other UDs and functional dies in embedded nonvolatile memory, such as OTPM/MTPM [17]....
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Patent•
19 Sep 2017TL;DR: A memristive neural network computing engine based on CMOS-compatible charge-trap transistor (CTT) is proposed and obtained a performance comparable to state-of-the-art fully connected neural networks using 8-bit fixed-point resolution.
Abstract: A neural network computing engine having an array of charge-trap-transistor (CTT) elements which are utilized as analog multipliers with all weight values preprogrammed into each CTT element as a CTT threshold voltage, with multiplicator values received from the neural network inference mode. The CTT elements perform computations of a fully connected (FC) neural network with each CTT element representing a neuron. Row resistors for each row of CTT element sum output currents as partial summation results. Counted pulse generators write weight values under control of a pulse generator controller. A sequential analog fabric (SAF) feeds multiple drain voltages in parallel to the CTT array to enable parallel analog computations of neurons. Partial summation results are read by an analog-to-digital converter (ADC).
5 citations
Cites background or methods from "80Kb 10ns read cycle logic Embedded..."
...Recently, charge-trap transistors (CTTs) were reported to be used as digital memory devices in [19-20] with reliable trapping and de-trapping behavior....
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...The trapped charge dissipates very slowly (> 8 years at 85 °C), allowing to be used for embedded nonvolatile memory [19]....
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...Due to the fast-reading and slow-writing nature of CTTs [19], it is desirable to store weights in the CTT threshold voltage and provide multiplicator values in the neural network inference mode, which does not require the change of weight values once they are programmed according to the pre-trained model....
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01 Apr 2017
TL;DR: Ramped programming optimization is investigated in order to limit the risk of gate oxide breakdown (BD) during the programming of a Multi-Time Programmable Memory.
Abstract: Ramped programming optimization is investigated in order to limit the risk of gate oxide breakdown (BD) during the programming of a Multi-Time Programmable Memory Optimization of the programming ramp rate has been proven to be beneficial at both device level and array level This allows for inline monitoring of programmability and BD-risk reduction as a function of process changes
1 citations
Cites methods from "80Kb 10ns read cycle logic Embedded..."
...The MTPM device used was presented in [1-3] with the memory cell illustrated in Figure 1....
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