90nm CMOS Low Power Multimodulus 32/33/39/40/47/48 Prescaler with METSPC Based Logic
29 Aug 2013-pp 243-247
TL;DR: A Modified Extended True Single Phase Clock (METSPC) based 2/3 prescaler design is presented and its operation is verified over all PVT variations with a max.
Abstract: The prescaler is primarily used in phased locked loop (PLL) to generate higher reference frequency for the loop, which supplies more samples per unit time to the phase detector to attain better frequency stability This paper is first to present a Modified Extended True Single Phase Clock (METSPC) based 2/3 prescaler design The METSPC-FF is fully investigated across all the process corners for power consumption and delay along with its functionality for GHz operations Both ETSPC and METSPC are compared to find that the PDP of METSPC is 6496% better than ETSPC Thus using METSPC enhances the operating performance of the prescaler A multimodulus 32/33/39/40/47/48 prescaler is proposed and its operation is verified over all PVT variations with a max frequency of 6GHz Simulation is performed in TSMC 90 nm technology using CADENCE SPECTRE simulator at supply voltage of 11V
Citations
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01 Oct 2018
TL;DR: A CMOS high speed frequency divider which can operate at up to 47GHz based on a chain of 2/3 prescaler using logic gate embedded RLTSPC D flip-flop is proposed to reduce circuit complexity and power consumption.
Abstract: This paper presents a CMOS high speed frequency divider which can operate at up to 47GHz based on a chain of 2/3 prescaler. A novel 2/3 prescaler structure using logic gate embedded RLTSPC D flip-flop is proposed minimized the critical delay to reach 47GHz. The following stage 2/3 prescaler is also optimized compared to conventional structure, to reduce circuit complexity and power consumption. The proposed frequency divider is implemented in 65nm CMOS process, and exhibits phase noise of -158.3 dBc/Hz@10MHz offset and power consumption of 1.3mW.
3 citations
Cites background from "90nm CMOS Low Power Multimodulus 32..."
...Therefore, a frequency divider with multi-division ratio is necessary [2]....
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01 Jan 2015
Cites background or methods from "90nm CMOS Low Power Multimodulus 32..."
...Diagram of multi-modulus 32/33/39/40/47/48 prescaler of [24] ....
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...Diagram of multi-modulus 32/33/39/40/47/48 prescaler of [24]...
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...The prescaler described in [24] is demonstrated in Figure 13....
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...28 High-speed prescaler designs are not necessarily limited to CML structures, and this fact is demonstrated in the work described in [24]....
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21 Jan 2012
Abstract: We have developed 90nm In0.7Ga0.3As channel HEMTs, directly measured of DC and RF characteristics, and performed microwave modeling for both 90nm Si CMOS and HEMT for benchmarking logic performance for future design layout and process improvement.
TL;DR: In this article , a power efficient 32/33 pre-scaler with adaptive voltage level source (AVLS) was proposed to reduce the power consumption of the D Flip-flops (D-FFs).
Abstract: Pre-scalers are widely used in phase-locked loops (PLL) which are vital components in communication systems. The Dual Modulus Pre-Scaler (DMPS) has dual division capability, to divide the clock by N/N+1 cycles, which can be controlled by the designer based on the control circuitry. Pre-scaler circuits are used to divide the received signal to obtain integer multiples of the received signal. This paper proposes a power efficient 32/33 pre-scaler for high-frequency operation. DMPS is composed of a series of D Flip-flops (D-FF) and logic gates along with feedback connection between the different stages. Clock skew is of major concern in the D-FFs, which can be reduced by realizing D-FFs using true single-phase clock (TSPC) logic. Furthermore, the incorporation of an Adaptive Voltage Level Source (AVLS) circuit decreases the power consumption of the circuits. By integrating the AVLS circuit to divide-by-32/33 DMPS, low power consumption is achieved. At different operating frequencies, both divide-by-32 and -33 modes of the proposed 32/33 DMPS with AVLS were analyzed. In comparison to the reference pre-scaler circuit, the proposed pre-scaler consumes 35.65% less power at 1GHz. CMOS 180nm technology in Cadence Virtuoso is used to realize circuits and Cadence Spectre is used to simulate circuits.
References
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TL;DR: A low-power divide-by-2/3 unit of a prescaler is proposed and implemented using a CMOS technology and, compared with the existing design, a 25% reduction of power consumption is achieved.
Abstract: The power consumption and operating frequency of the extended true single-phase clock (E-TSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the E-TSPC-based divider are calculated and simulated. A low-power divide-by-2/3 unit of a prescaler is proposed and implemented using a CMOS technology. Compared with the existing design, a 25% reduction of power consumption is achieved. A divide-by-8/9 dual-modulus prescaler implemented with this divide-by-2/3 unit using a 0.18-mum CMOS process is capable of operating up to 4 GHz with a low-power consumption. The prescaler is implemented in low-power high-resolution frequency dividers for wireless local area network applications
108 citations
"90nm CMOS Low Power Multimodulus 32..." refers methods in this paper
...A dynamic ETSPC flip flop is presented in [3], which avoids stacked MOS structure to overcome the body effect which is present in TSPC logic....
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TL;DR: A new low power and improved speed TSPC 2/3 prescaler is proposed which is silicon verified and capable of operating up to 5 GHz and ideally, a 67% reduction of power consumption is achieved when compared under the same technology at supply voltage of 1.8 V.
Abstract: In this paper the power consumption and operating frequency of true single phase clock (TSPC) and extended true single phase clock (E-TSPC) frequency prescalers are investigated. Based on this study a new low power and improved speed TSPC 2/3 prescaler is proposed which is silicon verified. Compared with the existing TSPC architectures the proposed 2/3 prescaler is capable of operating up to 5 GHz and ideally, a 67% reduction of power consumption is achieved when compared under the same technology at supply voltage of 1.8 V. This extremely low power consumption is achieved by radically decreasing the sizes of transistors, reducing the number of switching stages and blocking the power supply to one of the D flip-flops (DFF) during Divide-by-2 operation. A divide-by-32/33 dual modulus prescaler implemented with this 2/3 prescaler using a chartered 0.18 ?m CMOS technology is capable of operating up to 4.5 GHz with a power consumption of 1.4 mW.
95 citations
"90nm CMOS Low Power Multimodulus 32..." refers background or methods in this paper
...The prescalers are constructed with basic FF based on Current Mode Logic (CML) [4] which is victim of large load capacitance which results in inefficiency in terms of overall PDP metric....
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...True Single Phase Clock (TSPC) [4] based logic which extends current-drive capabilities and operating frequency compared to CML but because of stacked structure of transistor alignment, it was suffering from body effect....
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...Dual modulus prescalers, 2/3, 8/9 and 32/33 prescaler are presented in [4][5] using both TSPC and ETSPC logics....
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...The 2/3 prescaler architecture reported in [4], [6] has two NOR gates and two DFFs as in Fig....
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...[4] [5] [6] This work Process (nm) 180 65 180 90 Supply Voltage 1....
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TL;DR: A true-single-phase-clock (TSPC) divider synthesis technique that is based on the general TSPC logic family is introduced and the newly proposed RE-2 type has shown better balance between speed and power performance than other types.
Abstract: In this work, we introduce a true-single-phase-clock (TSPC) divider synthesis technique that is based on the general TSPC logic family. According to this unified technique, various types of TSPC dividers are compared in terms of the speed-power trade-off. The newly proposed RE-2 type has shown better balance between speed and power performance than other types. The measurement results of a prototype design in a 65 nm LP CMOS technology show that the maximal input frequencies can be 19 GHz and 16 GHz for a divide-by-2 divider and a divide-by-2/3 prescaler respectively, and the power consumption is less than 0.5 mW.
54 citations
TL;DR: A low-power single-phase clock multiband flexible divider for Bluetooth, Zigbee, and IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers is proposed based on pulse-swallow topology and is implemented using a 0.18-μm CMOS technology.
Abstract: In this paper, a low-power single-phase clock multiband flexible divider for Bluetooth, Zigbee, and IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers is proposed based on pulse-swallow topology and is implemented using a 0.18-μm CMOS technology. The multiband divider consists of a proposed wideband multimodulus 32/33/47/48 prescaler and an improved bit-cell for swallow (S) counter and can divide the frequencies in the three bands of 2.4-2.484 GHz, 5.15-5.35 GHz, and 5.725-5.825 GHz with a resolution selectable from 1 to 25 MHz. The proposed multiband flexible divider is silicon verified and consumes power of 0.96 and 2.2 mW in 2.4- and 5-GHz bands, respectively, when operated at 1.8-V power supply.
49 citations
"90nm CMOS Low Power Multimodulus 32..." refers background or methods or result in this paper
...compared to the multiband flexible divider (32/33/47/48 prescaler) at5GHz [6]....
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...This additional circuitry is used to perform div-by-39 and div-by-40 without any additional flip-flop as compared to [6]....
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...It is similar to multimodulus 32/33/47/48 prescaler proposed in [6], additionally it has a multiplexer, pair of AND gate and inverter....
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...The 2/3 prescaler architecture reported in [4], [6] has two NOR gates and two DFFs as in Fig....
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...[4] [5] [6] This work Process (nm) 180 65 180 90 Supply Voltage 1....
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08 Apr 1999
TL;DR: This research provides a clock power model for SoC that takes into account the impact of architectural, design, and logic style on clock power and will be used in designing the clock network and estimating its power dissipation.
Abstract: The paper investigates some issues on clock power consumption in system-on-a-chip (SoC) designs. Since clock power consumption is often the largest part of total chip power research in this area becomes urgent. In a SoC the clock depends not only on clock distribution wiring, clock driver sizing and the capability to disable part of the clock network, but also on circuit design style, architectural choice and the clock rate of the IP blocks. The different IP blocks may require that multiple-frequency clocks are distributed on the chip. Our research provides a clock power model for SoC that takes into account these various factors. The impact of architectural, design, and logic style on clock power is studied using adder and register designs. In research, such characterizing information on SoC designs will be used in designing the clock network and estimating its power dissipation.
33 citations
"90nm CMOS Low Power Multimodulus 32..." refers background in this paper
...This process is costliest because of high power consumption [1]....
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