A 0.6V 2.9µW mixed-signal front-end for ECG monitoring
01 Jun 2012-
TL;DR: A mixed-signal ECG front-end that uses aggressive voltage scaling to maximize power-efficiency and facilitate integration with low-voltage DSPs is presented in this paper, where a SAR ADC with a dual-DAC architecture eliminates the need for a power-hungry ADC buffer.
Abstract: This paper presents a mixed-signal ECG front-end that uses aggressive voltage scaling to maximize power-efficiency and facilitate integration with low-voltage DSPs. 50/60Hz interference is canceled using mixed-signal feedback, enabling ultra-low-voltage operation by reducing dynamic range requirements. Analog circuits are optimized for ultra-low-voltage, and a SAR ADC with a dual-DAC architecture eliminates the need for a power-hungry ADC buffer. Oversampling and ΔΣ-modulation leveraging near-V T digital processing are used to achieve ultra-low-power operation without sacrificing noise performance and dynamic range. The fully-integrated front-end is implemented in a 0.18µm CMOS process and consumes 2.9µW from 0.6V.
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TL;DR: A syringe-implantable electrocardiography (ECG) monitoring system is proposed that successfully detecting atrial fibrillation arrhythmia and storing the irregular waveform in memory in experiments using an ECG simulator, a live sheep, and an isolated sheep heart.
Abstract: A syringe-implantable electrocardiography (ECG) monitoring system is proposed. The noise optimization and circuit techniques in the analog front-end (AFE) enable 31 nA current consumption while a minimum energy computation approach in the digital back-end reduces digital energy consumption by 40%. The proposed SoC is fabricated in 65 nm CMOS and consumes 64 nW while successfully detecting atrial fibrillation arrhythmia and storing the irregular waveform in memory in experiments using an ECG simulator, a live sheep, and an isolated sheep heart.
149 citations
TL;DR: A low-power, reflectance-mode photoplethysmogram front end with up to 100 μA of static interferer current removal and 87 dB attenuation of time-varying interferers is presented.
Abstract: This paper presents a low-power, reflectance-mode photoplethysmogram (PPG) front end with up to 100 $\mu {\rm A}$ of static interferer current removal and 87 dB attenuation of time-varying interferers. The chip nominally consumes 425 $\mu {\rm W}$ including signal chain circuits, red and IR LED drive power, clocks, digitization and I/O. Measured data shows the noise of the PPG signal to be dominated by the photodiode sensor photon shot noise.
54 citations
TL;DR: A subdermal implantable, eight-channel EEG recorder and seizure detector that has two modes of operation: diagnosis and seizure counting, providing doctors with a reliable count to help determine medication efficacy or other clinical endpoint.
Abstract: EEG remains the mainstay test for the diagnosis and treatment of patients with epilepsy. Unfortunately, ambulatory EEG systems are far from ideal for patients who have infrequent seizures. These systems only last up to 3 days and if a seizure is not captured during the recordings, a definite diagnosis of the patient’s condition cannot be given. This work aims to address this need by proposing a subdermal implantable, eight-channel EEG recorder and seizure detector that has two modes of operation: diagnosis and seizure counting. In the diagnosis mode, EEG is continuously recorded until a number of seizures are recorded. In the seizure counting mode, the system uses a low-power algorithm to track the number of seizures a patient has, providing doctors with a reliable count to help determine medication efficacy or other clinical endpoint. An ASIC that implements the EEG recording and seizure detection algorithm was designed and fabricated in a 0.18 $\mu{\rm m}$ CMOS process. The ASIC includes eight EEG channels and is designed to minimize the system’s power and size. The result is a power-efficient analog front end that requires 2.75 $\mu{\rm W}$ per channel in diagnosis mode and 0.84 $\mu{\rm W}$ per channel in seizure counting mode. Both modes have an input referred noise of approximately 1.1 $\mu{\rm Vrms}$ .
41 citations
TL;DR: A sub- μW ECG acquisition IC is presented for a single-chamber leadless pacemaker applications that integrates a low-power, wide dynamic-range ECG readout front end together with an analog QRS-complex extractor.
Abstract: A sub- $\mu{\rm W}$ ECG acquisition IC is presented for a single-chamber leadless pacemaker applications. It integrates a low-power, wide dynamic-range ECG readout front end together with an analog QRS-complex extractor. To save ASIC power, a current-multiplexed channel buffer is introduced to drive a 7 b-to-10 b self-synchronized SAR ADC which utilizes 4 fF/unit capacitors. The ASIC consumes only 680nA and achieves CMRR $>$ 90 dB, PSRR $>$ 80 dB, an input-referred noise of 4.9 $\mu{\rm Vrms}$ in a 130 Hz bandwidth, and has rail-to-rail DC offset rejection. Low-power heartbeat detections are evaluated with the help of the ASIC acquiring nearly 20,000 beats across 10 different records from the MIT-BIH arrhythmia database. In the presence of muscle noise, both the average Sensitivity (Se) and Positive Predictivity (PP) show more than 90% when the input SNR $>$ 6 dB.
37 citations
06 Mar 2014
TL;DR: The presented analog signal processor (ASP) introduces a power-efficient analog feature extraction, a current-multiplexed ADC driver and a flexible ADC that enables low-power heartbeat detection for implantable pacemakers.
Abstract: Ultra-low power consumption and miniature size are by far the most important design requirements for implantable pacemakers. In order to guarantee a long life span of the device, saving power in the sensing IC is a primary concern as cardiac rhythm disorders must be continuously monitored [1]. Shifting the functionality of QRS-band power parameter extraction to the analog domain can reduce system-level power consumption of heartbeat detection significantly through minimizing computational complexity of the DSP [2,3]. In addition, current biomedical ICs still require further improvement of power efficiency as their analog back ends consume significant power [2-4]. For low-power means, the presented analog signal processor (ASP) introduces a power-efficient analog feature extraction, a current-multiplexed ADC driver and a flexible ADC. This advances the state of the art by reducing the power consumption of the ASP below 1μW without compromising other specs, such as input SNR >70dB, CMRR >90dB, PSRR >80dB, and enables low-power heartbeat detection for implantable pacemakers.
30 citations
References
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TL;DR: This paper describes a mixed-signal ECG System-on-Chip (SoC) that is capable of implementing configurable functionality with low-power consumption for portable ECG monitoring applications and can be reduced significantly.
Abstract: This paper describes a mixed-signal ECG System-on-Chip (SoC) that is capable of implementing configurable functionality with low-power consumption for portable ECG monitoring applications. A low-voltage and high performance analog front-end extracts 3-channel ECG signals and single channel electrode-tissue-impedance (ETI) measurement with high signal quality. This can be used to evaluate the quality of the ECG measurement and to filter motion artifacts. A custom digital signal processor consisting of 4-way SIMD processor provides the configurability and advanced functionality like motion artifact removal and R peak detection. A built-in 12-bit analog-to-digital converter (ADC) is capable of adaptive sampling achieving a compression ratio of up to 7, and loop buffer integration reduces the power consumption for on-chip memory access. The SoC is implemented in 0.18 $\mu$ m CMOS process and consumes 32 $\mu$ W from a 1.2 V while heart beat detection application is running, and integrated in a wireless ECG monitoring system with Bluetooth protocol. Thanks to the ECG SoC, the overall system power consumption can be reduced significantly.
193 citations
07 Apr 2011
TL;DR: This work presents a neural interface in 65nm CMOS and operating at a 0.5V supply that obtains performance comparable or superior to state-of-the-art systems in a silicon area over 3× smaller by using a scalable architecture that avoids on-chip passives and takes advantage of high-density logic.
Abstract: Recent success in brain-machine interfaces has provided hope for patients with spinal-cord injuries, Parkinson's disease, and other debilitating neurological conditions [1], and has boosted interest in electronic recording of cortical signals State-of-the-art recording solutions [2–5] rely heavily on analog techniques at relatively high supply voltages to perform signal conditioning and filtering, leading to large silicon area and limited programmability We present a neural interface in 65nm CMOS and operating at a 05V supply that obtains performance comparable or superior to state-of-the-art systems in a silicon area over 3× smaller These results are achieved by using a scalable architecture that avoids on-chip passives and takes advantage of high-density logic The use of 65nm CMOS eases integration with low-power digital systems, while the low supply voltage makes the design more compatible with wireless powering schemes [6]
182 citations
TL;DR: An overview of the basics of DDS, along with simple formulas to compute bounds of the signal characteristics, are given and several methods are presented to overcome some of the limits of the basic DDS with a focus on improving output signal quality.
Abstract: Oscillators are the subjects of intensive research. From Colpitts oscillators to phase locked loops, methods have been proposed to improve stability, frequency resolution, and spectral purity. Among the all-digital approaches, direct digital frequency synthesis are now available as integrated circuits and they output waveforms up to hundreds of megahertz. While DDS is slowly gaining acceptance in new system designs, methods used to improve the quality of the generated waveform are seldom used, even nowadays. The purpose of this article is to give an overview of the basics of DDS, along with simple formulas to compute bounds of the signal characteristics. Moreover, several methods, some patented, are presented to overcome some of the limits of the basic DDS with a focus on improving output signal quality.
127 citations
18 Mar 2010
TL;DR: The presented Analog Signal Processor (ASP) not only addresses the power efficient extraction of ECG signals, but also improves the state-of-the-art by providing a low-power means for both reducing the data rate ofECG signals through adaptive sampling and improving the robustness by monitoring motion artifacts.
Abstract: Power efficiency of readout circuits for ambulatory monitoring of biopotential signals has been significantly improved during recent years [1]–[3], leaving digital signal processing (DSP) and wireless transmission dominating the system power [4]. In addition, field tests have revealed that motion artifacts are a significant problem requiring even more processing power to differentiate between biological information and irrelevant motion artifacts. The presented Analog Signal Processor (ASP) not only addresses the power efficient extraction of ECG signals, but also improves the state-of-the-art by providing a low-power means for both reducing the data rate of ECG signals through adaptive sampling and improving the robustness by monitoring motion artifacts. It should be noted that these problems are traditionally being tackled in DSP increasing the system power. Referring to Figure 6.6.1, the ASP consists of an ECG readout channel, two quadrature readout channels for continuous-time (CT) monitoring of electrode-tissue impedance, two quadrature readout channels for tracking power fluctuations in a frequency band, and an activity detector (AD) that can sense the frequency content of the ECG signal and adapt the sampling rate of the integrated ADC.
67 citations