A 0.9–5.8-GHz Software-Defined Receiver RF Front-End With Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration
03 May 2017-IEEE Transactions on Very Large Scale Integration Systems (IEEE)-Vol. 25, Iss: 8, pp 2371-2382
TL;DR: A 0.9–5.8-GHz receiver RF front-end integrating a dual-band low-noise transconductance amplifier (LNTA), a passive harmonic-rejection down-conversion mixer, and an all-digital frequency synthesizer for software-defined radios are presented.
Abstract: A 0.9–5.8-GHz receiver RF front-end (RFE) integrating a dual-band low-noise transconductance amplifier (LNTA), a passive harmonic-rejection (HR) down-conversion mixer, and an all-digital frequency synthesizer for software-defined radios are presented. A switchable three-coil transformer acting as the interface between the LNTA and the mixer features current-gain boosting in addition to wideband operation. Automatic local oscillator phase-error detection and calibration circuitry is implemented for the mixers to achieve high HR ratio (HRR). Fabricated in 65-nm CMOS, the RFE measures the noise figure between 2.9 and 3.8 dB, the third-order input intercept point (IIP3) between −1.6 and −12.8 dBm, the third-order HRR of 81 dB, and the fifth-order HRR of 70 dB, while consuming 66–82 mA from a 1.2-V supply and occupying a chip area of 4.2 mm2.
Citations
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01 Aug 2020
TL;DR: In this paper, an active feedback CMOS LNA with balun function is integrated within a direct converter receiver, where the multi-gated transistor (MGTR) technique is employed to null the third-order distortion of the last two gain stages while complementary configurations are used to compensate secondorder nonlinearity in all stages.
Abstract: An inverter-based active feedback CMOS LNA with balun function is within a direct converter receiver. The LNA has three gain stages. The Multi-gated transistor (MGTR) technique is employed to null the third-order distortion of the last two gain stages while complementary configurations are used to compensate second-order nonlinearity in all stages. The complete direct-conversion receiver was fabricated in 28nm CMOS. Measurement results indicate that the integrated receiver provides a minimum NF of 3.4 dB, and a maximum gain of 48.2 dB from 1 to 6 GHz. The in-band and out-of-band IIP3 are -10 dBm and -4 dBm, respectively. The receiver dissipates 22.2 mW at 5 GHz LO frequency and occupies an area of 0.08 mm2.
13 citations
Cites background or methods from "A 0.9–5.8-GHz Software-Defined Rece..."
...In [6] a differential receiver uses a reconfigurable 3-coil transformer to cover from 0....
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...Unit GHz MHz dB dB dBm mm(2) mW nm Wu [6] 0....
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...Using reconfigurable passives [6] and [13] achieve similar RF bandwidths but occupy much larger area and require off-chip baluns....
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TL;DR: An interference-robust reconfigurable receiver in 65-nm CMOS is presented and a novel power-detection-based automatic frequency calibration technique is proposed to calibrate the operating frequency of the LNA in the HB path and overcome the effects of process, voltage, and temperature variations.
Abstract: An interference-robust reconfigurable receiver in 65-nm CMOS is presented. The front end is split into a low-band (LB) RF path (0.1–1.5 GHz) and a high-band (HB) RF path (1–5 GHz). By utilizing a harmonic recombination technique, the LB path could reject the third /fifth-order harmonic interferences. A tunable narrowband dual-feedback common-gate low-noise amplifier (LNA) with $LC$ resonant load provides second-order bandpass filtering to reject the harmonic interferences in the HB path. The RF high-Q bandpass filtering based on the voltage-mode passive mixer and the current-mode low-pass filter in the analog baseband improves the receiver’s resilience to out-of-band interferences. A novel power-detection-based automatic frequency calibration technique is proposed to calibrate the operating frequency of the LNA in the HB path and overcome the effects of process, voltage, and temperature variations. The presented receiver has been implemented in a 65-nm CMOS and consumes 20–76-mW power from 1.2-V power supplies, with a core die area of 5 mm2. The measured results show that the receiver can tolerate −5-dBm interference with 16-dB noise figure (NF) and achieve 95–105-dB maximum conversion gain and 1.7–8-dB NF over 0.1–5 GHz. It also achieves an average harmonic rejection (HR3)/HR5 of 61/68-dB, +7.1/+14.4 dBm in-band/out-of-band input third-order intercept point (OB-IIP3), +71.2-dBm OB-IIP2, and 58.1-dB-image rejection, after the digitally assisted calibrations. The system-level measurements show that the presented receiver achieves 2.1% error vector magnitude (EVM) for 850-MHz Global System for Mobile Communication signals and 5% EVM for band 42 time division duplexing-local thermal equilibrium (LTE) signals, respectively.
12 citations
TL;DR: SDR is a promising radio technology to increase the flexibility of radio devices and reduce hardware and manufacturing costs, chip size, and power consumption and is proposed to handle multiple bands through reconfiguration.
Abstract: The last decade has witnessed an increasing number of wireless standards for civil, military, and space communications. Along with the advances in integrated circuit (IC) technologies and the ever-growing requirements of high data rates, next-generation radios are expected to operate over multiple frequency bands. For example, carrier aggregation is used in LTE-Advanced radios to increase the bandwidth. However, it is challenging for traditional radios to operate over multiple frequency bands. In response to this, software-defined radios (SDRs) have been proposed to handle multiple bands through reconfiguration. They can adapt carrier frequency, transmission bandwidth, modulation, and encoding schemes by modifying digital signal processing (DSP) software algorithms [1]. In contrast to SDR, legacy communication systems are approaching their capability limits. They usually operate on a single band and require dedicated hardware. Thus, SDR is a promising radio technology to increase the flexibility of radio devices and reduce hardware and manufacturing costs, chip size, and power consumption [2].
10 citations
Cites background or methods from "A 0.9–5.8-GHz Software-Defined Rece..."
...Likewise, in [6], [38], and [73]–[75], transformers were used to vary the response of input matching to get a reconfigurable response....
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...Wideband LNAs Wideband LNAs provide a flat gain response across a wide range of frequencies for certain applications [6]....
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TL;DR: In this paper , the authors presented a 5.8 GHz highly sensitive, high-dynamic-range RF receiver front-end with Automatic-Gain Control (AGC) and a high image-rejection for a Dedicated Short-Range Communication (DSRC) application.
Abstract: This paper presents a 5.8 GHz highly sensitive, high-dynamic-range RF receiver front-end with Automatic-Gain Control (AGC) and a high image-rejection for a Dedicated Short-Range Communication (DSRC) application. It is formed by a transceiver common matching, a single to differential Low-Noise Amplifier (LNA), an active mixer with an Image Rejection Filter, and an AGC unit. The proposed AGC unit is composed of a power-detector over the intermediate-frequency signals of the downconverter mixer. The power detector produces a wide dynamic range response signal, which eases the controllability of the AGC unit. In addition, external components are minimized, and area occupation is optimized. The proposed RF-FE is fabricated and measured in a 130-nm RF CMOS process. Experimental results show an overall dynamic range of 77.6 dB while a high sensitivity performance to an input power level of −85 dBm is measured. An overall gain of 26.4 dB for the RF-FE is obtained. The input referred P1dB is measured to be around −28.3 dBm. The 2-stage RC poly-phase filter that is applied to reject the image signal results in a maximum image rejection ratio of 39 dB.
1 citations
References
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TL;DR: A closer look at the canonical functional partitioning of channel coding into antenna, RF, IF, baseband, and bitstream segments and a brief treatment of the economics and likely future directions of software radio technology are provided.
Abstract: As communications technology continues its rapid transition from analog to digital, more functions of contemporary radio systems are implemented in software, leading toward the software radio. This article provides a tutorial review of software radio architectures and technology, highlighting benefits, pitfalls, and lessons learned. This includes a closer look at the canonical functional partitioning of channel coding into antenna, RF, IF, baseband, and bitstream segments. A more detailed look at the estimation of demand for critical resources is key. This leads to a discussion of affordable hardware configurations, the mapping of functions to component hardware, and related software tools. This article then concludes with a brief treatment of the economics and likely future directions of software radio technology. >
2,002 citations
"A 0.9–5.8-GHz Software-Defined Rece..." refers background in this paper
...frequency range, ideal software-defined radios (SDRs) [1], [2] are a promising candidate to complement existing standarddedicated wireless transceivers....
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TL;DR: In this paper, a software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters.
Abstract: A software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in use today, a wideband RF front-end, including the low-noise amplifier (LNA) and a wide tuning-range synthesizer, spanning over 800 MHz to 6 GHz is designed. The wideband LNA provides 18-20 dB of maximum gain and 3-3.5 dB of noise figure over 800 MHz to 6 GHz. A low 1/f noise and high-linearity mixer is designed which utilizes the passive mixer core properties and provides around +70 dBm IIP2 over the bandwidth of operation. The entire receiver circuits are implemented in 90-nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards
433 citations
TL;DR: A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented and an accurate multiphase clock generator is presented for a mismatch-robust HR.
Abstract: A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative ?iterative? harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF, and + 3.5 dBm in-band IIP3 while the out-of-band IIP3 is +16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order HR > 60 dB over 40 chips, while the digital AIC technique achieves HR > 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply.
318 citations
"A 0.9–5.8-GHz Software-Defined Rece..." refers methods in this paper
...In [4], with a passive current-driven mixer using nonoverlapping LOs, out-of-band interference rejection was...
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14 Apr 2009
TL;DR: This paper considers the evolution of cognitive radio architecture (CRA) in the context of motivating use cases such as public safety and sentient spaces to characterize CRA with an interdisciplinary perspective where machine perception in visual, acoustic, speech, and natural language text domains provide cues to the automatic detection of stereotypical situations.
Abstract: The radio research community has aggressively embraced cognitive radio for dynamic radio spectrum management to enhance spectrum usage, e.g., in ISM bands and as secondary users in unused TV bands, but the needs of the mobile wireless user have not been addressed as thoroughly on the question of high quality of information (QoI) as a function of place, time, and social setting (e.g. commuting, shopping, or in need of medical assistance). This paper considers the evolution of cognitive radio architecture (CRA) in the context of motivating use cases such as public safety and sentient spaces to characterize CRA with an interdisciplinary perspective where machine perception in visual, acoustic, speech, and natural language text domains provide cues to the automatic detection of stereotypical situations, enabling radio nodes to select from among radio bands and modes more intelligently and enabling cognitive wireless networks to deliver higher QoI within social and technical constraints, made more cost effective via embedded and distributed computational intelligence.
294 citations
"A 0.9–5.8-GHz Software-Defined Rece..." refers background in this paper
...frequency range, ideal software-defined radios (SDRs) [1], [2] are a promising candidate to complement existing standarddedicated wireless transceivers....
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TL;DR: This paper describes the design and performance of a 90 nm CMOS SAW-less receiver with DigRF interface that supports 10 WCDMA bands and 4 GSM bands and results in current drain and die area savings as well as improved noise.
Abstract: This paper describes the design and performance of a 90 nm CMOS SAW-less receiver with DigRF interface that supports 10 WCDMA bands (I, II, III, IV, V, VI, VIII, IX, X, XI) and 4 GSM bands (GSM850, EGSM900, DCS1800, PCS1900). The receiver is part of a single-chip SAW-less transceiver reference platform IC for mass-market smartphones, which has been designed to meet Category 10 HSDPA (High Speed Downlink Packet Access) requirements. The novel receiver core consists of a single-stage transconductance amplifier (TCA) with large gain control range, a current commutating passive mixer enhanced for automatic on chip IIP2 calibration with 25% duty-cycle LO injection and threshold adjust, and current-input complex Direct Coupled Filter (DCF). The low noise TCAs are designed without inductive loads to save area. A self-contained on chip automatic IIP2 calibration system with algorithm routine, implemented in firmware, is used to optimize IIP2 performance. This topology eliminates the external LNA, inter-stage SAW filter and transimpedance amplifier (TZA) in conventional WCDMA designs and results in current drain and die area savings as well as improved noise. The 25% duty-cycle LO injection, with threshold adjustment, into a current driven passive double-balanced mixer results in 3 dB additional gain, lower noise figure and lower intermodulation distortion. Large signal blocking and 1/f noise performance are improved significantly by eliminating the 0 and 180deg LO signal crossover at the mixer. The full receiver achieves 2.2 dB/2.39 dB simplex/duplex NF (with - 24.5 dBm TX leakage), > 90 dBm complex two-tone IIP2, 60 dB gain and - 1/+ 5 dBm half/full-duplex image IIP3. The receiver core consumes only 15.1 mA from a 1.5 V supply.
210 citations
"A 0.9–5.8-GHz Software-Defined Rece..." refers methods in this paper
...To avoid performance degradation in terms of gain, NF, and linearity caused by simultaneously turning ON multiple mixing paths, nonoverlapping LO signals are used [7]–[9]....
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