A 1.2 V 285μA analog front end chip for a digital hearing aid in 0.13 μm CMOS
23 Dec 2013-pp 397-400
TL;DR: A low power analog front-end for a digital hearing aid, designed and fabricated in a 0.13μm CMOS process that accepts inputs from a microphone or telecoil, amplifies and digitizes it for processing by a DSP, accepts digital data from the D SP, converts it to analog form using a pulse width modulated class D amplifier, and drives the earpiece.
Abstract: We describe a low power analog front-end for a digital hearing aid, designed and fabricated in a 0.13μm CMOS process. The IC accepts inputs from a microphone or telecoil, amplifies and digitizes it for processing by a DSP, accepts digital data from the DSP, converts it to analog form using a pulse width modulated class D amplifier, and drives the earpiece, all over a 10kHz bandwidth. The programmable gain amplifier uses current sharing in the input stage to obtain low noise with low power consumption. The single-bit continuous-time ΔΣ ADC and the closed loop class-D amplifier use assisted opamp integrators to reduce power dissipation. An on chip ring oscillator provides the clock to the digital parts of the chip and to the digital signal processor (DSP). The chip has an input referred noise of 2.1μV, a dynamic range of 106 dB, an output THD of 0.006% and a peak output SNR of 79dB. It occupies 2.3 mm2 and consumes 285μA from a 1.2V supply.
Citations
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TL;DR: A high-resolution dual-integrating delta-sigma modulator (DI-DSM) for low-power analog front-end (AFE) circuits in biomedical instrumentation and the use of a lower switching frequency at the critical blocks results in a significant reduction in the power consumption of both the preamplifier and the modulator.
Abstract: This paper presents a high-resolution dual-integrating delta–sigma modulator (DI-DSM) for low-power analog front-end (AFE) circuits in biomedical instrumentation. The AFE contains a preamplifier and a switched-capacitor DS analog-to-digital converter. The proposed DI-DSM adopts two kinds of clock frequencies: one is the same as the conventional frequency and the other is one-half of the conventional frequency, which provides sufficient settling time for critical blocks. The proposed structure reduces harmonic distortions at the output of the preamplifier, since the preamplifier is given sufficient time to charge the sampling capacitor in the DSM. The use of a lower switching frequency at the critical blocks results in a significant reduction in the power consumption of both the preamplifier and the modulator. The proposed AFE chip is fabricated in a 65-nm CMOS process. The measurement results of the modulator show a peak signal-to-noise ratio (SNR) of 81.4 dB and a peak signal-to-noise-plus-distortion ratio (SNDR) of 80.4 dB, with a power consumption of 24.8 $\mu \text{W}$ at a supply voltage of 1 V and a signal bandwidth of 10 kHz. The complete AFE chip [which includes a preamplifier, a DI-DSM, a low-dropout (LDO) regulator, and a bandgap reference circuit (BGR)] shows a measured peak SNR of 79.3 dB and a measured peak SNDR of 77.0 dB with a preamplifier power of only 46.8 $\mu \text{W}$ (and 22.3 $\mu \text{W}$ for LDO, and 36.3 $\mu \text{W}$ for BGR).
17 citations
01 Nov 2016
TL;DR: This paper presents a 4-channel power electronics (PE) controller front-end interface with input signal conditioning and analog-to-digital (A/D) conversion functions for different power electronics system applications.
Abstract: This paper presents a 4-channel power electronics (PE) controller front-end interface with input signal conditioning and analog-to-digital (A/D) conversion functions for different power electronics system applications. The proposed front-end is composed of a 4-channel continuous-time (CT) and discrete-time (DT) hybrid sigma-delta modulator (H-EAM) embedding an input programmable-gain (PGA) in the first CT stage in order to enhance the input dynamic range (DR). The second shared DT stage is designed to utilize multiple-sampling technique with a shared single Op-Amp for low power consumption. This PE controller front-end chip is fabricated with 65 nm CMOS technology. Measurement results show a high dynamic range of 98.3 dB and 84.2 dB SNDR, while achieving a power consumption of 68 μW per channel and a FoMs of 172–179 dB due to the dynamic range boost.
9 citations
Additional excerpts
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TL;DR: A novel peak-statistical algorithm is proposed to track signal amplitude and adjust automatic gain control loop gain precisely and a hearing aid device prototype is produced that shows its great potential for mass manufacture in the future.
Abstract: For low-power hearing aid device application, a fully integrated optimized hearing aid SoC structure is proposed in this paper. The SoC consists of high-resolution, low-power analog front-end (AFE), time-division-multiplexed power-on-reset circuit, charge pump, digital signal processing (DSP) platform, and Class-D amplifier.
A novel peak-statistical algorithm is proposed to track signal amplitude and adjust automatic gain control loop gain precisely. A comparative DWA is applied to break the correlation of in-band tone and sequential selection scheme, which realizes second-order noise shaping and suppresses harmonic effectively. The SoC has been implemented with 0.13 µm CMOS process. By measurement, it shows that the peak signal-to-noise ratio (SNR) of AFE is 82.6 dB and peak SNR of Class-D amplifier is 79.8 dB. Also, three main algorithms of wide dynamic range compression, noise reduction, and feedback cancelation are executed through DSP platform. With 1 V supply voltage, total SoC power is 1.1 mW and core area is 9.3 mm2. Based on our SoC, a hearing aid device prototype is produced that shows its great potential for mass manufacture in the future.
9 citations
TL;DR: A novel peak-statistical algorithm and judgment logic PSJ for multifrequency signal application of Autogain Control Loop AGC in hearing aid SoC and the low-power circuit topology and noise-optimizing technique are adopted to improve the signal-to-noise ratio SNR.
Abstract: A novel peak-statistical algorithm and judgment logic PSJ for multifrequency signal application of Autogain Control Loop AGC in hearing aid SoC is proposed in this paper. Under a condition of multifrequency signal, it tracks the amplitude change and makes statistical data of them. Finally, the judgment is decided and the circuit gain is controlled precisely. The AGC circuit is implemented with 0.13 μm 1P8M CMOS mixed-signal technology. Meanwhile, the low-power circuit topology and noise-optimizing technique are adopted to improve the signal-to-noise ratio SNR of our circuit. Under 1 V voltage supply, the peak SNR achieves 69.2 dB and total harmonic distortion THD is 65.3 dB with 89 μW power consumption.
7 citations
22 May 2016
TL;DR: A prototype of hearing aid device is designed and passes the industrial acoustic test which shows the chip is promising for mass production in future.
Abstract: In this paper a full chip implementation of a Mixed-signal hearing aid SoC is presented. The chip integrates Analog Front-End (AFE), Time-Division Multiplexed Power-On-Reset circuit (TDM-POR), Charge Pump (CP), Digital Signal Processing (DSP) platform and Class-D amplifier. Also, the Low-Dropout (LDO) voltage regulators and On-chip oscillator are both integrated to minimize the system overall size. The proposed SoC has been fabricated in SMIC 0.13μm CMOS process. The measurement results show that the peak Signal-to-Noise Ratio (SNR) of AFE is 82dB and peak SNR of Class-D amplifier is 79.6dB. And the DSP platform executes three hearing-aid algorithms of wide dynamic range compression (WDRC), noise reduction (NR), and feedback cancellation (FDC). The total SoC consumes 1.1mA from single 1V supply and occupies 9.3mm2. Finally a prototype of hearing aid device is designed and passes the industrial acoustic test which shows the chip is promising for mass production in future.
7 citations
Cites background from "A 1.2 V 285μA analog front end chip..."
...Reference [3, 4] are analog hearing aid chips and don’t realize any configured noise reduction algorithm....
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References
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TL;DR: Frequency-compensation techniques of single-, two- and three-stage amplifiers based on Miller pole splitting and pole-zero cancellation are re-analyzed and several proposed methods to improve the published topologies are given.
Abstract: Frequency-compensation techniques of single-, two- and three-stage amplifiers based on Miller pole splitting and pole-zero cancellation are re-analyzed. The assumptions made, transfer functions, stability criteria, bandwidths, and important design issues of most of the reported topologies are included. Several proposed methods to improve the published topologies are given. In addition, simulations and experimental results are provided to verify the analysis and to prove the effectiveness of the proposed methods.
315 citations
TL;DR: A new high-speed, low-current levelshifter and a robust deadtime control arrangement are presented that are essential for a high quality switching power stage.
Abstract: An integrated stereo class-D audio power amplifier realized in a silicon-on-insulator (SOI)-based BCD technology is presented. The amplifier is capable of delivering 2/spl times/100 W in two 4-/spl Omega/ loads at a supply voltage of 60 V. A second-order feedback loop is used to suppress supply ripple and pulse-shape errors in the switching power stage. The limiting factor in the performance of any class-D amplifiers is the quality of the switching power stage. A high-speed low-current levelshifter and a robust deadtime control arrangement are proposed that enable the realization of a robust high-quality switching power stage. Some practical issues with respect to robustness and electromagnetic compatibility are discussed.
174 citations
TL;DR: The “assisted opamp” integrator is introduced, which is a way of achieving low distortion operation with low power consumption and circuit implementations of the technique for single-bit modulators using NRZ and switched-capacitor-resistor feedback DACs are presented.
Abstract: The opamp in the first integrator of a high resolution single-bit continuous-time modulator has stringent slew rate requirements, which increases power dissipation. We introduce the “assisted opamp” integrator, which is a way of achieving low distortion operation with low power consumption. We present circuit implementations of our technique for single-bit modulators using NRZ and switched-capacitor-resistor (SCR) feedback DACs. Audio modulators designed in a 0.18 μm CMOS technology are used as vehicles to demonstrate the effectiveness of our techniques. The modulator with an NRZ DAC achieves a dynamic range of 92.5 dB in a 24 kHz bandwidth and dissipates 110 μW from a 1.8 V supply. A second design, which employs an SCR-DAC, achieves a dynamic range of 91.5 dB and dissipates 122 μW. The figures of merit (FOM) of these modulators, 175.9 dB and 174.4 dB respectively, are comparable with those of state-of-the-art multibit designs.
84 citations
"A 1.2 V 285μA analog front end chip..." refers background in this paper
...3(a)) provide assistance [3] to the first opamp....
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TL;DR: A low-power energy-efficient adaptive analog front-end circuit is proposed and implemented for digital hearing-aid applications that adopts the combined-gain-control (CGC) technique for accurate preamplification and the adaptive-SNR (ASNR) technique to improve dynamic range with low power consumption.
Abstract: A low-power energy-efficient adaptive analog front-end circuit is proposed and implemented for digital hearing-aid applications. It adopts the combined-gain-control (CGC) technique for accurate preamplification and the adaptive-SNR (ASNR) technique to improve dynamic range with low power consumption. The CGC technique combines an automatic gain control and an exponential gain control together to reduce power dissipation and to control both gain and threshold knee voltage. The ASNR technique changes the value of the signal-to-noise ratio (SNR) in accordance with input amplitude in order to minimize power consumption and to optimize the SNR by sensing an input signal. The proposed analog front-end circuit achieves 86-dB peak SNR in the case of third-order /spl Sigma//spl Delta/ modulator with 3.8-/spl mu/Vrms of input-referred noise voltage. It dissipates a minimum and maximum power of 59.4 and 74.7 /spl mu/W, respectively, at a single 0.9-V supply. The core area is 0.5 mm/sup 2/ in a 0.25-/spl mu/m standard CMOS technology.
64 citations
TL;DR: A compressing preamplifier, ADC, DAC, output driver and clock oscillator are implemented in a mixed-signal BiCMOS hearing-aid chip with digital filtering.
Abstract: This paper presents a single-chip mixed-signal IC for a hearing aid system. The IC consumes 270 /spl mu/A of supply current at a 1.1-V battery voltage. The presented circuit and architectural design techniques reduce the total IC power to 297 /spl mu/W, a level where up to 70 days of lifetime is achieved at 10 h/day for a small zinc-air battery. The measured input referred noise for the entire channel is 2.8 /spl mu/Vrms and the average THD in the nominal operating region is 0.02%. The jitter for the on-board ring oscillator is 147 ps rms. The chip area is 12 mm/sup 2/ in a 0.6-/spl mu/m 3.3-V mixed-signal CMOS process.
51 citations