A 1.2 V, 33 ppm/°C, 40 nW, regeneration based BGR circuit for nanowatt CMOS LSIs
TL;DR: A regeneration based BGR circuit using positive feedback results in the positive temperature coeffecient of 2.34 mV/° C from the single stage at room temperature, which results in 60 % saving in power and over 80% saving in area, when compared with the state-of-the-art trimming less BGR circuits.
Abstract: A regeneration based BGR circuit is proposed in this paper. The regeneration using positive feedback results in the positive temperature coeffecient of 2.34 mV/° C from the single stage at room temperature. This results in 60 % saving in power and over 80 % saving in area, when compared with the state-of-the-art trimming less BGR circuits. The obtained temperature coefficient is 33 ppm/° C for the temperature range 0° C–90° C. The circuit is designed and simulated in UMC 180nm CMOS process. The circuit consumes power of 40 nW and occupies an area of 0.003 mm2. The reference voltage of 819 mV is achieved at 1.2 V power supply. The power supply rejection ratio at 40 kHz is −47 dB.
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177 citations
"A 1.2 V, 33 ppm/°C, 40 nW, regenera..." refers background in this paper
...Resistor-less BGR circuits are reported in [1], [2]....
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...Parameters [1] [2] [3] This work Process [nm] 180 180 350 180...
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...In [1], the complement to absolute temperature (CTAT) with negative temperature coefficient (NTC) of approximately -2 mV/◦C is compensated by multiple proportional to absolute temperature (PTAT) stages of 0....
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49 citations
"A 1.2 V, 33 ppm/°C, 40 nW, regenera..." refers background or methods in this paper
...Resistor-less BGR circuits are reported in [1], [2]....
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...In [2], an additional processing circuit is used to increase the accuracy of BGR circuit....
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...Parameters [1] [2] [3] This work Process [nm] 180 180 350 180...
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10 citations
"A 1.2 V, 33 ppm/°C, 40 nW, regenera..." refers methods in this paper
...0015% [4] by using proper layout techniques like interdigitization and the common-centroid....
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