736 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 5, MAY 1997
A 1.8-GHz Low-Phase-Noise CMOS VCO
Using Optimized Hollow Spiral Inductors
Jan Craninckx, Student Member, IEEE, and Michiel S. J. Steyaert, Senior Member, IEEE
Abstract— A completely integrated 1.8-GHz low-phase-noise
voltage-controlled oscillator (VCO) has been realized in a stan-
dard silicon digital CMOS process. The design relies heavily
on the integrated spiral inductors which have been realized
with only two metal layers and without etching. The effects of
high-frequency magnetic fields and losses in the heavily doped
substrate have been simulated and modeled with finite-element
analysis. The achieved phase noise is as low as
0
116 dBc/Hz
at an offset frequency of 600 kHz, at a power consumption of
only 6 mW. The VCO is tuned with standard available junction
capacitances, resulting in a 250-MHz tuning range.
Index Terms—CMOS analog integrated circuit, integrated in-
ductor, phase noise, voltage-controlled oscillator.
I. INTRODUCTION
D
UE to the ever-growing importance of the mobile
telecommunications market, the need for small, cheap,
and low-power RF circuit components cannot be underes-
timated. By putting more and more functions on the same
die, the feasibility of the single-chip transceiver has already
been demonstrated [1]–[4]. One of the major challenges in
the design of a cheap transceiver system is the frequency
synthesis of the local oscillator (LO) signal.
Indeed, the specs for, e.g., the GSM or DCS-1800 system,
require the ability to detect very small signals while very
strong unwanted signals are present in the adjacent channels.
If the LO signal in the receiver path has too much power at
frequencies away from the wanted carrier signal, these strong
interfering signals will also be mixed down, which will result
in a contamination of the wanted received signal. A similar
problem arises in the transmit path [5].
Frequency synthesis is usually done using a phase-locked
loop (PLL). The general block diagram of a PLL is shown in
Fig. 1. The feedback action in the loop causes the output fre-
quency to be
times the reference frequency. This reference
signal can be generated by a very stable, low-frequency crystal
oscillator. The spectral purity of the synthesized signal will
largely depend on the quality of the VCO signal [6]. Therefore,
to ensure a LO with very low phase noise, a high-quality LC-
tank is needed for the oscillator. Up to now, RF designers
always had to use some external elements for this tank. If the
required specs can be achieved with an internal LC-tank, this
will aid in designing a low-cost transceiver system.
Manuscript received August 14, 1996; revised November 9, 1996.
The authors are with the Department Elektrotechniek, afd. ESAT-MICAS,
Katholieke Universiteit Leuven, B-3001 Heverlee, Belgium.
Publisher Item Identifier S 0018-9200(97)03414-8.
Fig. 1. PLL-based frequency synthesizer.
More recently, the possibilities of standard CMOS technolo-
gies for RF telecommunication circuit blocks have been proven
in the design of low-noise amplifiers (LNA’s) [7], down-
conversion mixers [8], upconvertors [9], voltage-controlled
oscillators (VCO’s) [10], prescalers [11], [12], etc. Since the
baseband signal processing is also done in this cheap tech-
nology, these designs have proven CMOS to be a promising
candidate as the technology for future single-chip transceiver
IC’s.
This paper presents a VCO design which uses integrated
planar inductors in the resonance LC-tank, so no external ele-
ments are necessary. Moreover, a standard CMOS technology
has been used with only two metal layers and a heavily doped
substrate. The combination of these two aspects makes this a
worst-case technology for designing VCO’s, since only two
metal layers means the spiral inductor will have a large series
resistance compared to three- or four-level technologies, and
the induced currents in the heavily doped substrate are an
important source of extra losses.
The possibilities for and problems associated with silicon
integrated inductors are discussed in Section II. To accurately
quantify the losses present in spiral inductors, a finite-element
simulation strategy is used. The results obtained are analyzed
in Section III. The oscillator circuit design is discussed in
Section IV. Finally, Sections V and VI give the measured
performance and some conclusions.
II. S
ILICON INTEGRATED INDUCTORS
The key to the design of a low-phase-noise oscillator is a
high-quality inductor [13]. Unlike capacitors, inductors are not
readily available in a standard CMOS technology. As a result,
some design tricks have to be used, which usually limit the
performance of the inductor.
Active inductors use some active elements to transform the
impedance of a capacitor to an inductive impedance. High-
frequency operation is possible [14], and the fact that the
inductance can be tuned is very advantageous in the design of
a VCO. However, the noise generated by the active elements
0018–9200/97$10.00 1997 IEEE
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CRANINCKX AND STEYAERT: 1.8-GHz LOW-PHASE-NOISE CMOS VCO 737
(a) (b)
Fig. 2. Spiral inductor layout: (a) square and (b) octagonal.
requires the use of an excessive amount of power to achieve
low-noise specs [13].
Recently, the feasibility of oscillators based on the induc-
tance of a bondwire has been proven. The very low series
resistance of gold bondwires allows the achievement of the un-
matched phase noise performance of
115 dBc/Hz at 200 kHz
offset from the 1.8-GHz carrier [10]. Bondwires are readily
available in any IC technology, and can therefore be regarded
as being a standard CMOS technology feature. However,
because manufacturers cannot guarantee issues such as yield
or repeatability of the bonding process, the semiconductor
industry is still hesitant to use this technique.
The only option left is to lay out a rectangular spiral
metal trace on the silicon substrate, using one or more of the
standard metal interconnection levels available, as shown in
Fig. 2(a). The basics for the inductance calculation of these
planar inductors were developed by Greenhouse in 1974 [15].
If the technology allows 45
routing, an octagonal shape can
be used [Fig. 2(b)]. Of course, a lot of parasitic effects limit
the possible applications of spiral coils.
The quality factor of the inductor will be limited by the
series resistance of the metal traces. Typical values in a simple
process are 15
for a 10-nH inductor [16]. GaAs circuits,
which incorporate a lot of planar inductors, have the advantage
of gold interconnects to achieve low series resistance. In
silicon, most designers use very wide metal turns and several
routing levels in a multilayer process to obtain a low series
resistance [17], [18]. However, we will show in the next
section that due to high-frequency magnetic field effects (such
as the well-known skin effect), this is not necessarily the best
solution.
One of the most recognized parasitics is the capacitance
to the substrate. Together with the wanted inductance, this
gives an LC resonance frequency above which the coil can no
longer be used as an inductor. A typical value for the self-
resonance frequency is 2.5 GHz for a 10-nH inductor [16].
This puts a limit on the maximal inductance value achievable
at a certain frequency, as larger inductors require a larger area
and thus also a larger capacitance and a smaller self-resonance
frequency. Special processing technologies exist that create
an air-gap underneath the inductor, or have very thick oxide
under their top metal routing level [19]. The resulting smaller
parasitic capacitance allows higher operating frequencies.
More recently, another solution for the self-resonance prob-
lem has been developed. By using selective etching techniques,
the silicon substrate can be removed in a post-processing step
from underneath the inductor, either by etching from the top of
the wafer [20], [21], or from the back of the wafer [17]. This
removes the capacitance to the substrate, and shifts the self-
resonance frequency of a 100-nH inductor from 0.8 GHz to
3 GHz [20]. But more important, this technique also eliminates
the resistive losses in the substrate. However, this requires
extra nonstandard processing steps, and as a result, the industry
is very hesitant to adopt those techniques.
The resistive losses in the substrate are indeed the most
important limitation in using planar inductors in a standard
CMOS process. Most bipolar or BiCMOS technologies use a
lowly doped substrate, resulting in a substrate resistivity in the
order of 10
cm. Most submicron CMOS technologies how-
ever use epiwafers. They consist of a lowly doped epilayer,
in which the transistors are situated on top of a heavily doped
substrate. The resistivity in the substrate is in the order of
0.01
cm. The reason for this low resistance is to diminish
the effects of hot-electron induced substrate currents, prevent
digital circuits from disturbing sensitive analog circuits, etc.
A large drawback of these heavily doped substrates is the fact
that now currents in the substrate, which are generated by the
magnetic field of the inductor, are free to flow, as will be
shown by the finite-element simulations in Section III-B. This
severely increases the losses and reduces the inductance value.
III. F
INITE-ELEMENT SIMULATIONS
The goal of this design is to prove the feasibility of planar
inductors for the design of standard CMOS VCO’s. The
technology used has only two metal layers and a heavily
doped substrate. Post-processing is not accepted by industry,
and etching the substrate away underneath the inductor cannot
be regarded as being a standard CMOS technology. To make
a completely monolithic standard CMOS VCO, the effect of
the conductive substrate must be included in the design.
From the discussion in the previous section, we can con-
clude that spiral inductors suffer from three parasitic effects.
First, parasitic capacitance to the substrate causes the inductor
to self-resonate at a certain frequency. Second, the high-
frequency series resistance will differ from the calculated one
due to skin effect and other magnetic field effects. Third, the
losses in the heavily doped substrate cause a large degradation
in the overall quality factor and reduce the inductance value.
In order to better understand these effects, an efficient
simulation strategy has been used. Simulation is necessary
because the problem is much too complex to be solved
analytically. The only way to fully simulate all the effects is a
full three-dimensional (3-D) finite-element simulation. That is,
however, very time-consuming. We want to gain some insight
in the severity of the several parasitic effects as a function of
coil geometry by simulating many different coils. This should
lead to some general design guidelines for planar inductors.
Therefore, simulation must be done as fast as possible. Planar
two-dimensional (2-D) or so-called 2.5-D simulators work
very fast and can operate on complex coil geometries. But
these are not sufficient for the problem, because they do not
account completely for the substrate effects.
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738 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 5, MAY 1997
Fig. 3. Cross section of a circular inductor.
We have chosen to simulate circular inductors instead of
square coils. Circular inductors offer the advantage of being
symmetrical around the vertical axis, and the problem therefore
only has a 2-D complexity. Two-dimensional simulation can be
done very fast. The simulated structure is shown in Fig. 3. The
coil has
metal turns, an outer radius , conductor width ,
and spacing
between the conductors. The substrate consists
of a heavily doped bulk material, a lowly doped epilayer, and
an n-well (or p-well) layer. On top of this is the field oxide.
A current of a certain frequency is forced through the coil,
and the resulting magnetic field and all resistive losses are
calculated. This simulation was done with the commercially
available program MagNet [22] and takes approximately 10 to
15 min per inductor. This gives us a very fast way to calculate
the inductance and the equivalent series resistance of several
coil geometries. We can make a distinction between losses in
the metal conductors and losses in the silicon. That way, we
can gain insight in the several parasitic effects in the metal
conductors and in the substrate. The conclusions drawn from
these simulations are now discussed.
A. Metal Losses
At low frequencies, the series resistance of the metal con-
ductor traces can easily be calculated as the product of the
sheet resistance and the number of squares of the metal
trace. At high frequencies, however, the skin effect and
other magnetic field effects will cause a nonuniform current
distribution in the inductor. This will have a (sometimes
serious) influence on the losses in the metal conductor at high
frequencies.
The best known of these effects is the skin effect. It can
be analyzed analytically for a straight metal conductor with
circular cross section. Instead of using the full area for current
flow, the current is pushed to the outside of the conductor
at high frequencies. This is shown schematically in Fig. 4. A
skin depth
is defined as being the equivalent thickness of a
hollow conductor that has the same high-frequency resistance
(1)
with
the magnetic permeability of the material, the
resistivity, and
the frequency of interest. In the planar
inductor, this effect can no longer be calculated analytically,
but it is clearly seen in the finite-element simulations.
Fig. 4. Skin effect in a straight conductor with circular cross section.
Fig. 5. Influence of the skin effect on planar inductors.
As an example, two inductor geometries are simulated, one
with parameters
m, m, m,
and one with parameters
m, m,
m. So the second inductor has metal turns which are
twice as wide as the first one. The radius has been adjusted
in order to achieve approximately the same inductance value.
The wide metal turns should allow a low series resistance
and hence low phase noise in the oscillator. Due to the larger
radius
, the resistor ratio is not as large as two, but equals
1.67. Since the phase noise of an LC-oscillator is proportional
to the equivalent series resistance of the LC-tank [13], a
dB better phase noise performance is
possible with the second coil. Fig. 5 shows the variation of
the metal series resistance as a function of frequency. The
ratio
is drawn, i.e., the ratio between the effective
series resistance at a certain frequency and the resistance at
dc. At 2 GHz, the series resistance of the second inductor (2)
is already 60% higher than the value at dc, while the first one
(1) only suffers a 30% increase. Therefore, the difference in
resistance between the two inductors is now only a factor 1.35,
or 1.3 dB. The inductance value remains roughly unchanged
for both. At even higher frequencies, the resistance increase
is enormous.
This proves that inductors using very wide metal turns are
not the way to go in designing low-phase-noise oscillators.
Due to the larger required coil radius when using wide turns
to maintain the inductance value, the phase noise does not
decrease linearly with conductor width. This is even enhanced
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CRANINCKX AND STEYAERT: 1.8-GHz LOW-PHASE-NOISE CMOS VCO 739
TABLE I
I
NDIVIDUAL SERIES RESISTANCE PER METAL TRACE
Fig. 6. Individual series resistance per metal trace.
by the skin effect which seriously deteriorates the series
resistance of wide conductors at high frequencies.
If we look at the individual resistance of each metal turn,
we notice another, even more important, effect. Normally, we
should expect a high resistance at the outer turns, because they
are the longest, which then gradually decreases for the inner
turns. However, an unexpected dependence results from the
finite-element simulations. An inductor with parameters
m, m, and m was simulated at
several frequencies. Table I gives, as a function of frequency,
the inductance value
, the total metal series resistance ,
and the individual resistance
of each turn. is the
resistance of the outer turn,
the innermost one. Fig. 6 gives
a 3-D graphical representation of the data in Table I. This data
shows that at high frequencies, the largest contribution to the
series resistance does not come from the longer outer turns,
but from the inner turns!
increases from 1.03 at low
frequencies to 1.21
at 2 GHz, or by 18%. The increase
in
is from 0.16 to 0.95 , or 480%! This enormous
difference cannot be explained by the skin effect in a single
metal trace alone, since both traces are of equal width and
they should suffer to the same amount from the nonuniform
current distribution.
The cause for this phenomenon can be found in the gen-
eration of eddy currents in the inner conductors, as shown in
Fig. 7. Generation of eddy currents in planar inductors.
Fig. 7. A part of the right half of the circular inductor is shown
schematically, from the outer turn 1 to the inner turn 9. The
inductor carries a current
, which flows in the direction as
indicated in the outer turns in the figure. This current of course
has an associated magnetic field
, which has a maximum
intensity in the center of the coil. The magnetic field is oriented
perpendicular to the page, in the direction coming out of the
page (indicated by the symbol
).
When the spiral inductor is filled with turns up to the center
of the coil, a large part of the magnetic field does not pass
through the center of the coil but goes through those inner
turns. Due to the time-varying nature of the coil current, the
generated magnetic field
also varies with time. According
to the law of Faraday–Lenz, an electrical field is magnetically
induced in the inner turns that will generate circular eddy
currents
as indicated in Fig. 7. The direction of these
eddy currents is such that they oppose the original change in
magnetic field. So the magnetic field
resulting from the
eddy currents has a direction flowing into the page (indicated
by the symbol
). The magnitude of the induced electrical
field is proportional to the derivative of
to time, so the
effect is only noticed at high frequencies. As the total magnetic
field (
) will be smaller, the inductance value
will decrease at high frequencies, as noticed in Table I.
These eddy currents again cause a nonuniform current flow
in the inner coil turns. On the inner side of the inner turn, coil
current
and eddy current flow in the same direction,
so the current density is larger than average. At the outer
side, both currents cancel and the current density is smaller
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740 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 5, MAY 1997
than average. As a result, the current in the inner turns is
pushed to the inside of the conductor. This can clearly be seen
when analyzing the results of the finite-element simulation. In
extreme conditions, the magnitude of the eddy currents is even
larger than the coil current, making the current density on the
outside of the inner turn negative, i.e., current is flowing in
the “wrong” direction.
One might be able to prevent these eddy currents to flow
by making longitudinal stripes in the inner conductors, or
perhaps by making the inner turns less wide than the outer
ones. However, the effects of such countermeasures are ques-
tionable, since they will result in a higher dc resistance of the
inner turns. These turns already have a low contribution to
the inductance because of the small area they enclose, so even
without the eddy currents they cause a (slight) deterioration of
the overall quality factor. So it is best if the inner turns are
completely omitted, i.e., one should leave a hole in the middle
of the spiral coil.
To conclude the discussion on the losses in the metal
conductors of a planar inductor, we can safely say that the
interactions of skin effect and eddy currents seem far too
complex to be analyzed analytically, so the only possible
solution to predict the high-frequency metal series resistance
is finite-element simulation. As a general rule, it can be stated
that conductor width should be limited because of the skin
effect, but most important, a “hollow” coil should be used. The
inner turns already have a low contribution to the inductance,
because of the small area they enclose, and they suffer from
an incredible increase in series resistance due to eddy currents
at high frequencies. In order to prevent deterioration of the
overall quality factor of the inductor, they must be left out
of the coil.
B. Substrate Losses
As stated earlier, a major drawback of most submicron
CMOS technologies is the use of epiwafers which have a
heavily doped substrate. In these substrates, currents induced
by the magnetic field of the inductor are free to flow, which is
the cause for extra resistive losses and a decrease in inductance
value.
This is show in Fig. 8. This figure schematically shows a
vertical cross section of the inductor, including the underlying
substrate. At the projected instance of time, the inductor
current
flows into the page on the right (symbol ) and out of
the page on the left (symbol
). As for the eddy currents in the
inner conductors, here the law of Faraday–Lenz implies that
an electrical field is magnetically induced in an imaginary coil
in the substrate underneath the inductor. Therefore, a current
will flow in the substrate. The direction of this induced
current is such that it opposes the original change in magnetic
field. So it flows in a direction opposite to the current in the
inductor, as indicated in the figure.
In a substrate with a high resistivity, the induced electrical
field only causes a small amount of current
to flow, and
the effect of the substrate currents can be neglected [16]. The
quality factor of the inductor is than completely determined by
the losses in the metal conductors. Finite-element simulations
Fig. 8. Generation of substrate currents on planar inductors.
Fig. 9. Resistive losses in the metal traces and in the substrate for planar
inductors on heavily doped substrates.
of coils in such a process indicate that values larger than ten
can be achieved.
In our case, the losses in the heavily doped substrate
prevent the realization of such high quality factors. This is
demonstrated in Fig. 9. A coil with four turns, having a width
m and spacing m, is simulated at a frequency
of 2 GHz for different radii
. Fig. 9 shows the metal series
resistance
and the silicon series resistance . This is
an equivalent series resistance which models the losses of
the induced substrate currents. As the length of the metal
trace becomes longer,
increases gradually. The silicon
losses show a completely different curve. For small coils, the
metal losses dominate, so the quality factor will be determined
by
. For the largest coil, the metal resistance is 12.1 ,
whereas the silicon resistance is increased to a value as large
as 20.7
. Without the silicon losses, the quality factor would
be
GHz nH . This is decreased to
only five due to the substrate currents. At lower frequencies,
the effect is less severe since the changes in the magnetic field
are slower.
The inductance value
also suffers from the substrate
currents. Since these currents flow in the opposite direction
from the current in the coil, the total magnetic field magnitude
will be smaller. Since the inductance value can be defined
as the ratio between total magnetic flux and coil current, the
inductance of the coil will be reduced. For the largest coil with
radius
m, the substrate currents decrease the value
of
with approximately 10%.
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