A 1.8 V 3.2 /spl mu/W comparator for use in a CMOS imager column-level single-slope ADC
23 May 2005-pp 6162-6165
TL;DR: Using this comparator design, the power consumption of column-level single-slope ADC of a CMOS imager can be reduced significantly.
Abstract: In this paper, a 1.8 V 3.2 /spl mu/W comparator is presented. It features a hybrid offset compensation scheme and achieves over 60 dB gain with an input offset below 150 /spl mu/V. The comparator is designed in a 0.18 /spl mu/m CMOS process and is specifically designed to be used as the key component of a column-level single-slope ADC of a CMOS imager. This ADC architecture is attractive because of its low noise, but so far this has come at the price of a relatively high power consumption. Using this comparator design, the power consumption of column-level single-slope ADC can be reduced significantly.
Citations
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TL;DR: In this paper, a column-level fixed-pattern noise reduction technique called dynamic column switching (DCS) is proposed to reduce the perceptual effects of nonuniformities introduced by column-wise circuit elements.
Abstract: This paper presents a CMOS imager with column-level ADC that uses a dynamic column fixed-pattern noise (FPN) reduction technique. This technique, called dynamic column switching (DCS), strongly reduces the perceptual effects of nonuniformities introduced by the column-level ADC or any other column-wise circuit element. This relaxes the uniformity requirements on the column-level ADC circuitry, which can significantly decrease power consumption and chip area. The proposed DCS technique requires only five transistors per column and minimal digital overhead at the chip level. A prototype was realized in a 0.18 mum CMOS process. The implemented column-level ADC uses a single-slope architecture and features a low-power column circuit design. In the measured images, the application of dynamic column switching make a column FPN of plusmn0.67% of full scale nearly invisible to the human eye
69 citations
Patent•
21 Dec 2007TL;DR: In this article, an analog signal is converted to a digital value having a given number of bits that define given quantization levels, by repeatedly sampling the analog signal at a resolution that is less than that which is defined by the given numbers of bits.
Abstract: An analog signal is converted to a digital value having a given number of bits that define given quantization levels, by repeatedly sampling the analog signal at a resolution that is less than that which is defined by the given number of bits. Lower resolution sampling results are thereby obtained. The lower resolution sampling results are summed to obtain the digital value having the given number of bits.
31 citations
TL;DR: The effectiveness of recently-reported techniques for extended-dynamic-range CISs is clarified and the FoM defined by (noise)2(power)/(intrascene dynamic range)(pixel-rate) separately for low/middle and high pixel-rate regions well explains the frontline of the CIS’ performance in all the pixel rates.
Abstract: This paper reviews architectures and topologies for column-parallel analog-to-digital converters (ADCs) used for CMOS image sensors (CISs) and discusses the performance of CISs using columnparallel ADCs based on figures-of-merit (FoM) with considering noise models which behave differently at low/middle and high pixel-rate regions. Various FoM considering different performance factors are defined. The defined FoM are applied to surveyed data on reported CISs using columnparallel ADCs which are categorized into 4 types; single slope, SAR, cyclic and delta-sigma ADCs. The FoM defined by (noise)2(power)/(pixel-rate) separately for low/middle and high pixel-rate regions well explains the frontline of the CIS’ performance in all the pixel rates. Using the FoM defined by (noise)2(power)/(intrascene dynamic range)(pixel-rate), the effectiveness of recently-reported techniques for extended-dynamic-range CISs is clarified. key words: CMOS image sensor, column-parallel ADC, cyclic ADC, deltasigma modulation, single-slope ADC, SAR ADC, figure of merit
23 citations
TL;DR: A reconfigurable, highly time-interleaved ADC architecture that substantially decouples comparator requirements from input signal bandwidth and system sampling rate constraints is presented and achieves sub 400 fJ/step in all configurations and a near flat SFDR over the entire input signal frequency range.
Abstract: A reconfigurable, highly time-interleaved ADC architecture that substantially decouples comparator requirements from input signal bandwidth and system sampling rate constraints is presented. A highly parallel array of low bandwidth, single slope converters achieves low noise and high linearity with very low input capacitance and signal-independent current consumption. A 128-channel counter ADC, implemented in 0.13 μm CMOS, can be configured in real-time as a 1 GSps 7-bit, 500 MSps 8-bit, or 250 MSps 9-bit converter. Central to this approach is a novel parallel slope ramp-generator based on a rotating figure-of-8 resistor ring. The ADC achieves sub 400 fJ/step in all configurations and a near flat SFDR over the entire input signal frequency range. The figure of merit scales favourably to nanometer CMOS technologies.
22 citations
Cites background from "A 1.8 V 3.2 /spl mu/W comparator fo..."
...Commonly in counter based converters clock or dynamic [14] or continuous time [15] comparators can be used....
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20 May 2012
TL;DR: This work proposes an off-line calibration scheme where the offset error is quantized by successive approximation, and improves the robustness of this cancellation by using a redundant cell to compensate for any internal mismatch within the DAC.
Abstract: This paper describes a fully dynamic analog comparator with digital calibration for very low offset error. In this work, we propose an off-line calibration scheme where the offset error is quantized by successive approximation. During run-time, the offset is cancelled by a digital-to-analog converter (DAC). We further improve the robustness of this cancellation by using a redundant cell to compensate for any internal mismatch within the DAC. Simulation in 0.18 um CMOS technology shows that our scheme can reduce the offset error to less than 0.86 mV rms under 1.8 V supply. The comparator consumes 1.4 pJ, and the clock to data delay is 3.5 ns.
19 citations
Cites background from "A 1.8 V 3.2 /spl mu/W comparator fo..."
...Since this type of dynamic comparators does not allow any analog feedback, it is impossible to perform analog auto-zeroing in [4]....
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References
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TL;DR: A 500MSam- ple/s 6-Bit ADC and its embedded implementation inside a disk drive read channel, using a 0.35µm CMOS single-poly, triple-metal process, achieves better than 5 effective number of bits (ENOB) for input frequencies up to Nyquist frequency and sampling frequencies fsup to 400MHz.
Abstract: The analog-to-digital conversion required in most disk-drive read-channel applications is designed for good dynamic and noise performance over a wide-input frequency range. This paper presents a 500-MSample/s, 6-bit analog to-digital converter (ADC) and its embedded implementation inside a disk-drive read channel, using a 0.35-/spl mu/m CMOS double-poly (only one poly layer was used in the ADC), triple-metal process. The converter achieves better than 5 effective number of bits (ENOB) for input frequencies up to Nyquist frequency (f/sub in/=f/sub s//2) and sampling frequencies f/sub s/ up to 400 MHz. It also achieves better that 5.6 ENOB for input frequencies up to f/sub s//4 over process, temperature, and power-supply variations. At maximum speed (f/sub s/=500 MHz), the converter still achieves better than 5 ENOB for input frequencies up to f/sub in/=200 MHz. Low-frequency performance is characterized by DNL<0.32 LSB and INL<0.2 LSB. The converter consumes 225 mW from a 3.3-V supply when running at 300 MHz and occupies 0.8 mm/sup 2/ of chip area.
87 citations
01 Jan 1998
TL;DR: A 500MSam- ple/s 6-Bit ADC and its embedded implementation inside a disk drive read channel, using a 0.35µm CMOS single-poly, triple-metal process, achieves better than 5 effective number of bits (ENOB) for input frequencies up to Nyquist frequency and sampling frequencies f s up to 400MHz.
Abstract: The analog-to-digital conversion required in most disk drive read channel applications is designed for good dynamic and noise performance over a wide input frequency range. This paper presents a 500MSam- ple/s 6-Bit ADC and its embedded implementation inside a disk drive read channel, using a 0.35µm CMOS single-poly, triple-metal process. The converter achieves better than 5 effective number of bits (ENOB) for input frequencies up to Nyquist frequency (f in = 1/2f s ) and sampling frequencies f s up to 400MHz. It also achieves better that 5.6 ENOB for input frequencies up to 1/4f s over process, temperature and power supply variations. At maximum speed (f s = 500MHz) the converter still achieves better than 5 ENOB for input frequencies up to f in = 200MHz. Low frequency performance is characterized by DNL < 0.38LSB and INL < 0.2LSB. The converter consumes 225mW from a 3.3V supply when running at 300MHz and occupies 0.8mm2of chip area.
61 citations
09 Feb 2003
TL;DR: In this paper, a 30 frames/s SXGA 5.6 /spl mu/m pinned photodiode pixel column parallel CMOS image sensor achieves 340 /spl µ/V noise floor and 40 pA/cm/sup 2/ dark current.
Abstract: A 30 frames/s SXGA 5.6 /spl mu/m pinned photodiode pixel column parallel CMOS image sensor achieves 340 /spl mu/V noise floor and 40 pA/cm/sup 2/ dark current. Performance is limited by pixel 1/f noise, not by the ADC noise floor of 140 /spl mu/V. The column ADC memory employs a custom DRAM to save area. The sensor utilizes a 0.35 /spl mu/m 1P 3M CMOS process.
34 citations
"A 1.8 V 3.2 /spl mu/W comparator fo..." refers background or result in this paper
...60mW in [1] and 20mW in [ 2 ] (the latter number is recalculated to VGA resolution at 30 frames/second)....
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...In Fig. 1, a possible approach for a column-level ADC is depicted [ 2 ]....
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...In contrast, it has been shown [ 1-3 ] that a column-parallel ADC can offer a significantly lower noise, as each ADC channel has a much lower bandwidth....
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01 Jan 2003
20 citations
"A 1.8 V 3.2 /spl mu/W comparator fo..." refers background in this paper
...60mW in [1] and 20mW in [2] (the latter number is recalculated to VGA resolution at 30 frames/second)....
[...]
...In contrast, it has been shown [1-3] that a column-parallel ADC can offer a significantly lower noise, as each ADC channel has a much lower bandwidth....
[...]
...1, a possible approach for a column-level ADC is depicted [2]....
[...]