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Journal Articleโ€ขDOIโ€ข

A 1.9-GHz, 1-W CMOS class-E power amplifier for wireless communications

01 Jul 1999-IEEE Journal of Solid-state Circuits (IEEE)-Vol. 34, Iss: 7, pp 962-970
TL;DR: In this article, a 1-W, class-E power amplifier is implemented in a 0.35-/spl mu/m CMOS technology and suitable for operations up to 2 GHz.
Abstract: This paper presents a 1-W, class-E power amplifier that is implemented in a 0.35-/spl mu/m CMOS technology and suitable for operations up to 2 GHz. The concept of mode locking is used in the design, in which the amplifier acts as an oscillator whose output is forced to run at the input frequency. A compact off-chip microstrip balun is also proposed for output differential-to-single-ended conversion. At 2-V supply and at 1.98 GHz, the power amplifier achieves 48% power-added efficiency (41% combined with the balun).
Citations
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Journal Articleโ€ขDOIโ€ข
TL;DR: In this paper, an identity obtained from phase and envelope equations is used to express the requisite oscillator nonlinearity and interpret phase noise reduction, and the behavior of phase-locked oscillators under injection pulling is also formulated.
Abstract: Injection locking characteristics of oscillators are derived and a graphical analysis is presented that describes injection pulling in time and frequency domains. An identity obtained from phase and envelope equations is used to express the requisite oscillator nonlinearity and interpret phase noise reduction. The behavior of phase-locked oscillators under injection pulling is also formulated.

1,159ย citations

Journal Articleโ€ขDOIโ€ข
TL;DR: In this article, the performance of the newly introduced distributed active transformer (DAT) structure to that of conventional on-chip impedance-transformations methods is analyzed, and a 2.4-GHz 1.9-W 2-V fully integrated power-amplifier achieving a power-added efficiency of 41% with 50/spl Omega/ input and output matching has been fabricated using 0.35-/spl mu/m transistors.
Abstract: In this paper, we compare the performance of the newly introduced distributed active transformer (DAT) structure to that of conventional on-chip impedance-transformations methods. Their fundamental power-efficiency limitations in the design of high-power fully integrated amplifiers in standard silicon process technologies are analyzed. The DAT is demonstrated to be an efficient impedance-transformation and power-combining method, which combines several low-voltage push-pull amplifiers in series by magnetic coupling. To demonstrate the validity of the new concept, a 2.4-GHz 1.9-W 2-V fully integrated power-amplifier achieving a power-added efficiency of 41% with 50-/spl Omega/ input and output matching has been fabricated using 0.35-/spl mu/m CMOS transistors.

444ย citations


Cites methods from "A 1.9-GHz, 1-W CMOS class-E power a..."

  • ...Until now, the highest output powers achieved by fully integrated power amplifiers in standard silicon processes are 85 mW [1] delivered to a differential 50- load with a power-added efficiency (PAE) of 30% and 100 mW with a drain efficiency of 16% [2], both implemented in CMOS technology....

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Journal Articleโ€ขDOIโ€ข
05 Feb 2001
TL;DR: In this paper, a highly integrated 175 GHz 035/spl ยต/m CMOS transmitter is described, which facilitates integration through the use of a unique mixer, termed a harmonic-rejection mixer, and a wide loop bandwidth phase-locked loop (PLL) for the RF synthesizer.
Abstract: A highly integrated 175-GHz 035-/spl mu/m CMOS transmitter is described The I/Q modulator-based transmitter facilitates integration through the use of a unique mixer, termed a harmonic-rejection mixer, and a wide loop bandwidth phase-locked loop (PLL) for the RF synthesizer The harmonic-rejection mixers are used to eliminate the need for a discrete IF filter and the use of a wide loop bandwidth PLL allowed for the complete integration of the synthesizers using low-Q components while achieving low phase noise The entire transmit signal path from the digital-to-analog converters to the power amplifier, including two fully integrated frequency synthesizers, is integrated into a single-chip solution The transmitter was tested with a testing buffer before the power amplifier (PA) and achieved less than 13/spl deg/ rms phase error when modulating a DCS-1800 GMSK signal The prototype consumed 151 mA from a 3-V supply A class-C PA, capable of driving 25 dBm off-chip, was included and the output was compared to the testing buffer with little change in the transmitter performance

433ย citations

Journal Articleโ€ขDOIโ€ข
TL;DR: In this article, a distributed active transformer is presented to combine several low-voltage push-pull amplifiers efficiently with their outputs in series to produce a larger output power while maintaining a 50/spl Omega/match.
Abstract: A novel on-chip impedance matching and power-combining method, the distributed active transformer is presented. It combines several low-voltage push-pull amplifiers efficiently with their outputs in series to produce a larger output power while maintaining a 50-/spl Omega/ match. It also uses virtual ac grounds and magnetic couplings extensively to eliminate the need for any off-chip component, such as tuned bonding wires or external inductors. Furthermore, it desensitizes the operation of the amplifier to the inductance of bonding wires making the design more reproducible. To demonstrate the feasibility of this concept, a 2.4-GHz 2-W 2-V truly fully integrated power amplifier with 50-/spl Omega/ input and output matching has been fabricated using 0.35-/spl mu/m CMOS transistors. It achieves a power added efficiency (PAE) of 41 % at this power level. It can also produce 450 mW using a 1-V supply. Harmonic suppression is 64 dBc or better. This new topology makes possible a truly fully integrated watt-level gigahertz range low-voltage CMOS power amplifier for the first time.

411ย citations


Cites methods from "A 1.9-GHz, 1-W CMOS class-E power a..."

  • ...Multiple external components such as bonding wires and external baluns have been used as tuned elements to produce output power levels in excess of 1 W using CMOS [1], [2] or Si-Bipolar transistors [3], [4]....

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Journal Articleโ€ขDOIโ€ข
TL;DR: In this article, a new family of switching amplifiers, each member having some of the features of both class E and inverse F, is introduced, which have class-E features such as incorporation of the transistor parasitic capacitance into the circuit.
Abstract: A new family of switching amplifiers, each member having some of the features of both class E and inverse F, is introduced. These class-E/F amplifiers have class-E features such as incorporation of the transistor parasitic capacitance into the circuit, exact truly switching time-domain solutions, and allowance for zero-voltage-switching operation. Additionally, some number of harmonics may be tuned in the fashion of inverse class F in order to achieve more desirable voltage and current waveforms for improved performance. Operational waveforms for several implementations are presented, and efficiency estimates are compared to class-E.

302ย citations

References
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Bookโ€ข
01 Apr 1990

10,459ย citations

Journal Articleโ€ขDOIโ€ข
TL;DR: In this article, a load network is synthesized to have a transient response which maximizes power efficiency even if the active device switching times are substantial fractions of the a.c. cycle.
Abstract: The new class of amplifiers described is based on a load network synthesized to have a transient response which maximizes power efficiency even if the active device switching times are substantial fractions of the a.c. cycle. The new class of amplifiers, named `Class E,' is defined and is illustrated by a detailed description and a set of design equations for one simple member of the class. For that circuit the authors measured 96 percent transistor efficiency at 3.9 MHz at 26-W output from a pair of Motorola 2N3735 TO-5 transistors. Advantages of Class E are unusually high efficiency, a priori designability, large reduction in second-breakdown stress, low sensitivity to active-device characteristics, and potential for high-efficiency operation at higher frequencies than previously published Class-D circuits.

1,902ย citations

01 Jan 1975
TL;DR: Advantages of Class E are unusually high efficiency, a priori designability, large reduction in second-breakdown stress, low sensitivity to active-device characteristics, and potential for high-efficiency operation at higher frequencies than previously published Class-D circuits.

1,396ย citations


"A 1.9-GHz, 1-W CMOS class-E power a..." refers background in this paper

  • ...Fig. 1 shows a conceptual picture of a class-E power amplifier [ 7 ], [8]....

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Journal Articleโ€ขDOIโ€ข
TL;DR: In this paper, the Fourier series analysis of the collector voltage waveform is used to determine component values for optimum operation at an efficiency of 100 percent, and other combinations of component values and duty cycles are also determined.
Abstract: The class E tuned power amplifier consists of a load network and a single transistor that is operated as a switch at the carrier frequency of the output signal. The most simple type of load network consists of a capacitor shunting the transistor and a series-tuned output circuit, which may have a residual reactance. Circuit operation is determined by the transistor when it is on, and by the transient response of the load network when the transistor is off. The basic equations governing amplifier operation are derived using Fourier series techniques and a high- Q assumption. These equations are then used to determine component values for optimum operation at an efficiency of 100 percent. Other combinations of component values and duty cycles which result in 100-percent efficiency are also determined. The harmonic structure of the collector voltage waveform is analyzed and related amplifier configurations are discussed. While this analysis is directed toward the design of high-efficiency power amplifiers, it also provides insight into the operation of modern solid-state VHF-UHF tuned power amplifiers.

962ย citations

Journal Articleโ€ขDOIโ€ข
TL;DR: In this article, a digital modulation for future mobile radio telephone services is proposed, and its fundamental properties are clarified with the aid of machine computation, and the constitution of modulator and demodulator is discussed from the viewpoints of mobile radio applications.
Abstract: This paper is concerned with digital modulation for future mobile radio telephone services. First, the specific requirements on the digital modulation for mobile radio use are described. Then, premodulation Gaussian filtered minimum shift keying (GMSK) with coherent detection is proposed as an effective digital modulation for the present purpose, and its fundamental properties are clarified with the aid of machine computation. The constitution of modulator and demodulator is then discussed from the viewpoints of mobile radio applications. The superiority of this modulation is supported by some experimental test results.

720ย citations


"A 1.9-GHz, 1-W CMOS class-E power a..." refers methods in this paper

  • ...To verify its potential in practical communication applications, the mode-locking class-E PA was tested with a Gaussian minimum shift keying (GMSK) [ 21 ] modulated input signal....

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