A 100 mA Low Voltage Linear Regulators for Systems on Chip Applications Using 0.18 μm CMOS Technology

TLDR: A new design methodology to choosing the right LDO to power each cell phone and especially for the Voltage Phase-Locked loops (VPLLs) blocks is provided.

Abstract: A novel design for a low dropout (LDO) voltage regulator is presented and dedicated to power many sections of a typical cellular handset. However, these baseband, RF, and audio sections have different requirements that influence which LDO is most appropriate. After discussion of the specific requirements, different LDOs are recommended. Also, some LDO design techniques are briefly discussed to demonstrate how an LDO may be optimized for a specific level of performance. Cellular phone designs require linear regulators with low-dropout, low-noise, high PSRR, low quiescent current (Iq), and low-cost. They need to deliver a stable output and use small-value output capacitors. Ideally, one device would have all these characteristics and one low-dropout linear regulator (LDO) could be used anywhere in the phone without worry. But in practice, the various cell phone blocks are best powered by LDOs with different performance characteristics. This paper provides a new design methodology to choosing the right LDO to power each cell phone and especially for the Voltage Phase-Locked loops (VPLLs) blocks. Fabricated in a 0.18 µm CMOS process, the measured results show the adopted topology achieves a better phase noise than the conventional saturation current source. and the spread of the current limitation (without matching) is 100mA, the VPLLs system demonstrates a phase noise of 782 nv/sqrtHz at 100-kHz, and 33 nv/sqrtHz at 1 MHz, while quiescent current 33 µA from a 2.6 V supply voltage.