A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3- mu m CMOS
TL;DR: A self-calibrated pipelined A/D converter technique potentially appropriate for high-resolution video applications that requires much less area than multistep flash approaches and requires fewer clock cycles than error averaging techniques.
Abstract: Described is a self-calibrated pipelined A/D converter technique potentially appropriate for such high-resolution video applications. This approach requires much less area than multistep flash approaches and requires fewer clock cycles than error averaging techniques. Since self-calibration can be performed during interframe intervals, this approach is particularly attractive for video applications. A 3- mu m CMOS prototype fabricated using this architecture achieves 13-b resolution at 2.5 Msample/s. consumes 100 mW, and occupies 40 kmil/sup 2/ (26 mm/sup 2/), with a single 5-V supply and two-phase nonoverlapping clock. >
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15 Feb 1995
TL;DR: In this paper, the authors briefly cover case studies in the use of direct-conversion receivers and transmitters and summarizes some of the key problems in their implementations, which arise from more appropriate circuit design and exploiting system characteristics, such as the modulation format in the system.
Abstract: Direct-conversion is an alternative wireless receiver architecture to the well-established superheterodyne, particularly for highly integrated, low-power terminals. Its fundamental advantage is that the received signal is amplified and filtered at baseband rather than at some high intermediate frequency. This means lower current drain in the amplifiers and active filters and a simpler task of image-rejection. There is considerable interest to use it in digital cellular telephones and miniature radio messaging systems. This paper briefly covers case studies in the use of direct-conversion receivers and transmitters and summarizes some of the key problems in their implementations. Solutions to these problems arise not only from more appropriate circuit design but also from exploiting system characteristics, such as the modulation format in the system. Baseband digital signal processing must be coupled to the analog front-end to make direct-conversion transceivers a practical reality.
1,060 citations
TL;DR: In this paper, a 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6/spl mu/m CMOS technology.
Abstract: A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6 /spl mu/m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 11.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW.
966 citations
Cites methods from "A 13-b 2.5-MHz self-calibrated pipe..."
...This array could be set either manually or automatically with a self-calibration scheme [ 9 ]....
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TL;DR: This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 /spl mu/m CMOS technology which achieves a power dissipation of 35 mW at full speed operation.
Abstract: This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 /spl mu/m CMOS technology which achieves a power dissipation of 35 mW at full speed operation. Circuit techniques used to achieve this level of power dissipation include digital correction to allow the use of dynamic comparators, and optimum scaling of capacitor values through the pipeline. Also, to be compatible with low voltage mixed-signal system environments, a switched capacitor (SC) circuit in each pipeline stage is implemented and operated at 3.3 V with a new high-speed, low-voltage operational amplifier and charge pump circuits. Measured performance includes 0.6 LSB of INL, 59.1 dB of SNDR (Signal-to-Noise-plus-Distortion-Ratio) for 100 kHz input at 20 Msample/s. At Nyquist sampling (10 MHz input) SNDR is 55.0 dB. Differential input range is /spl plusmn/1 V, and measured input referred RMS noise is 220 /spl mu/V. The power dissipation at 1 MS/s is below 3 mW with 58 dB of SNDR. >
623 citations
Proceedings Article•
01 Jan 1995
TL;DR: In this article, the authors describe a 10 b, 20 µm pipeline A/D converter implemented in 1.2 μm CMOS technology which achieves a power dissipation of 35 mW at full speed operation.
Abstract: ―This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 μm CMOS technology which achieves a power dissipation of 35 mW at full speed operation. Circuit techniques used to achieve this level of power dissipation include digital correction to allow the use of dynamic comparators, and optimum scaling of capacitor values through the pipeline. Also, to be compatible with low voltage mixed-signal system environments, a switched capacitor (SC) circuit in each pipeline stage is implemented and operated at 3.3 V with a new high-speed, low-voltage operational amplifier and charge pump circuits. Measured performance includes 0.6 LSB of INL, 59.1 dB of SNDR (Signal-to-Noise-plus-Distortion-Ratio) for 100 kHz input at 20 Msample/s. At Nyquist sampling (10 MHz input), SNDR is 55.0 dB. Differential input range is ± 1 V, and measured input referred RMS noise is 220 μV. The power dissipation at 1 MS/s is below 3 mW with 58 dB of SNDR.
577 citations
TL;DR: In this paper, a 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9-mu m CMOS technology is described, which uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a SNDR of 60 dB with a full-scale sinusoidal input at 5 MHz.
Abstract: A 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9- mu m CMOS technology is described. The converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-and-distortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies a 8.7 mm/sup 2/ and dissipates 240 mW. >
570 citations
References
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TL;DR: A self-calibrating analog-to-digital converter using binary weighted capacitors and resistor strings is described and 15-bit resolution and linearity at a 12-kHz sampling rate is demonstrated.
Abstract: A self-calibrating analog-to-digital converter using binary weighted capacitors and resistor strings is described. Linearity errors are corrected by a simple digital algorithm. A folded cascode CMOS comparator resolves 30 /spl mu/V in 3 /spl mu/s. An experimental converter fabricated using a 6-/spl mu/m-gate CMOS process demonstrates 15-bit resolution and linearity at a 12-kHz sampling rate.
360 citations
01 Jan 1990
TL;DR: A 10-b BiCMOS analog-to-digital converter (ADC) is used to demonstrate a current-mode pipeline system that overcomes some of the limitations of high-speed multiple-flash architectures.
Abstract: A 10-b BiCMOS analog-to-digital converter (ADC) is used to demonstrate a current-mode pipeline system that overcomes some of the limitations of high-speed multiple-flash architectures. Although multistage ADCs are efficient in both die area and power, a track-and-hold amplifier (T/H) is required to prevent the input from changing while a conversion is taking place. If the ADC is pipelined (operating on more than one sample at a time), a T/H is required between each pipeline stage. Additionally, for resolution greater than about 8 b interstage amplification is required. The settling behavior of the T/Hs and amplifiers dominates the performance of these ADCs. To address these problems, a differential current-mode architecture incorporates current-mode T/Hs, obviating the need for interstage amplifiers. The prototype chip achieves 10 b of resolution at 20 Msample/s with an 80-MHz input bandwidth and dissipates 1 W. >
45 citations
01 Jan 1988
TL;DR: A differential CMOS pipelined ADC that achieves a throughput rate of lMHz with 12b linearity and errors resulting from capacitor mismatch and switch feedthrough are corrected in analog domain without using digital calibration and/or trimming.
Abstract: A CAPACITOR-ERROR AVERAGING TECHNIQUE t o perform an accurate multiply-by-two (x2) function is required in high-resolution pipelined ADCs. Errors resulting from capacitor mismatch and switch feedthrough are corrected in analog domain without using digital calibration and/or trimming. This report will describe a differential CMOS pipelined ADC that achieves a throughput rate of lMHz with 12b linearity. The ADC is a serial converter composed of cascaded l b ADCs; Figure 1. It has a high throughput rate with relatively little circuitry. It has been proposed as an ADC architecture for sampled-data circuits’-3, and is different from another pipelined multi-step ADC4. Each stage performs the same function of sampling the output of a previous stage and multiplying it by 2. A reference voltage Vref is subtracted from this doubled input, and the result is compared t o zero. If positive, the bit is “1” and it is sampled by the following staage. However, if negative, the bit is “0” and the reference voltage is added by switching back t o the ground before it is sampled by the following stage. A sampled analog voltage is therefore pipelined to determine the digital bits sequentially starting from the most significant bit. An extra clock phase for adding a reference voltage back when the bit is “0” is unnecessary if a negative reference voltage -Vref is used instead of Vref in the subsequent bit decision. The basic function of multiply-by-two and reference subtraction to obtain 2Vin -Vref is implemented with a differential circuit shown in Figure 2, which uses only two pairs of identical capacitors. In the sampling phase, both input and operational amplifier offset are sampled on two capacitors. In the next amplifying phase, one of the capacitors is connected in the feedback loop, and the other is connected to a reference voltage. At this time, the reference voltage is either V,,f or -Vref, and the output voltage becomes 2Vin Vref or 2Vin t V,,f for the previous bit decision of “1” or “0”, respectively. Errors in switched-capacitor pipelined converters arise from capacitor mismatch. MOS switch feedthrough, sampled wideband
18 citations