A 14.2 mW 2.55-to-3 GHz Cascaded PLL With Reference Injection and 800 MHz Delta-Sigma Modulator in 0.13 $\mu$ m CMOS
TL;DR: In this paper, a low-noise cascaded PLL is proposed where an integer-N digital bang-bang P LL is used to multiply a 50 MHz reference to an 800 MHz clock that is fed to a ΔΣ fractional-N PLL to generate 2.55-to-3 GHz output.
Abstract: In this paper, a low-noise cascaded PLL is proposed where an integer-N digital bang-bang PLL is used to multiply a 50 MHz reference to an 800 MHz clock that is fed to a ΔΣ fractional-N PLL to generate 2.55-to-3 GHz output. In order to minimize the jitter of the 800 MHz clock, a reference injection scheme using dual-pulse ring oscillator is employed. Quantization noise from the delta-sigma modulator is suppressed without any noise cancellation techniques owing to the high operating frequency of the fractional-N PLL. Prototype implemented in 0.13 μm CMOS process achieves the worst-case RMS jitter of 356 fsrms over 100 Hz to 40 MHz integration bandwidth, while consuming 14.2 mW from a 1.2 V supply. The worst-case fractional spur measured over 7 different chips is -53.9 dBc and the reference spur is -84 dBc.
Citations
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TL;DR: This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor.
Abstract: This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented using digital standard cells without any modification, and automatically Place-and-routed (P&R) by a digital design flow without any manual placement. Implemented in a 65 nm digital CMOS process, this work occupies only 110 μm × 60 μm layout area, which is the smallest PLL reported so far to the best knowledge of the authors. The measurement results show that this work achieves a 1.7 ps RMS jitter at 900 MHz output frequency while consuming 780 μW DC power.
124 citations
TL;DR: In this paper, a quadrature fractional-N cascaded frequency synthesizer and its phase noise analysis, optimization, and design for future 5G wireless transceivers are theoretically presented and verified with measured results.
Abstract: This paper introduces a quadrature fractional-N cascaded frequency synthesizer and its phase noise analysis, optimization, and design for future 5G wireless transceivers. The performance improvement of the cascaded phase-locked loop (PLL) over single-stage PLL in terms of jitter and power consumption is theoretically presented and verified with measured results. The cascaded PLL is implemented using a first-stage fractional-N charge-pump PLL followed by a second-stage quadrature dividerless subsampling PLL. The fractional division in the first-stage PLL is implemented using a high-resolution phase mixer for lower quantization noise. Two prototypes of the single-stage PLL and the cascaded PLL were implemented in the 65-nm bulk CMOS process. The 26–32 GHz quadrature cascaded PLL consumes a total of 26.9 mW from 1-V supply and achieves less than 100-fs integrated jitter with −116.2 and −112.6-dBc/Hz phase noise at 1-MHz offset for the integer-N and the fractional-N modes, respectively. The fractional-N single-stage and cascaded PLLs achieve figure-of-merits of −230.58 and −248.75 dB, respectively.
71 citations
TL;DR: This paper presents the first published multiplying delay-locked loop achieving fine fractional-N frequency resolution, and introduces an automatic cancellation of the phase detector offset, by insertion of a digital-to-time converter in the reference path.
Abstract: Although multiplying delay-locked loops allow clock frequency multiplication with very low phase noise and jitter, their application has been so far limited to integer-N multiplication, and the achieved reference-spur performance has been typically limited by time offsets. This paper presents the first published multiplying delay-locked loop achieving fine fractional-N frequency resolution, and introduces an automatic cancellation of the phase detector offset. Both capabilities are enabled by insertion of a digital-to-time converter in the reference path. The proposed synthesizer, implemented in a standard 65 nm CMOS process, occupies a core area of 0.09 mm $^{2}$ , and generates a frequency ranging between 1.6 and 1.9 GHz with a 190 Hz resolution from a 50 MHz quartz-based reference oscillator. In fractional-N mode, the integrated RMS jitter, including random and deterministic components, is below 1.4 ps at 3 mW power consumption, leading to a jitter-power figure of merit of $-$ 232 dB. In integer-N mode, the circuit achieves RMS jitter of 0.47 ps at 2.4 mW power and figure of merit of $-$ 243 dB. Thanks to the adoption of the automatic offset cancellation, the reference-spur level is reduced from $-$ 32 to $-$ 55 dBc.
60 citations
Cites methods from "A 14.2 mW 2.55-to-3 GHz Cascaded PL..."
...They entail either the realization of an additional feedback loop detecting the time offset and retiming the injected pulse [13], [24], [26]–[28], or the adoption of techniques aiming to decouple the feedback of the PLL loop from the reference injection (such as the dual-pulse oscillator in [14], [34], or the dual loop in [29])....
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TL;DR: A 2.8-3.2-GHz fractional-N digital PLL, implemented in 0.18- μm CMOS, is presented, and achieves 230-fs rms jitter, integrated from a 1-kHz to 40-MHz offset, while drawing 17 mW from a1-V supply.
Abstract: A 2.8-3.2-GHz fractional-N digital PLL, implemented in 0.18- μm CMOS, is presented. The PLL architecture has the form of a classic delta-sigma fractional-N PLL. A PFD generates up and down pulses from the reference and divided-down digitally controlled oscillator (DCO) clock. The time-to-digital converter (TDC) converts the width of up pulses to digital words. The quantization noise introduced by a third-order delta-sigma modulator through the multi-modulus divider is canceled at the TDC output. A resistively interpolated ADC is employed to boost TDC resolution by a factor of five. A dither-less DCO with an inductively coupled fine-tuned varactor bank improves tuning step-size by a factor of 16.6, to 20 kHz. With a 52-MHz reference clock, a 3.2-GHz output clock, and a loop-bandwidth of 950 kHz, this prototype achieves 230-fs rms jitter, integrated from a 1-kHz to 40-MHz offset, while drawing 17 mW from a 1.8-V supply. The in-band phase noise floor is -111.6 dBc/Hz at a 500-kHz offset. The reference spur is -75 dBc and the worst-case fractional-N spur, by sweeping the multiplication ratio near 61, is -55 dBc. An FOM of -240.4 dB is achieved, and this design occupies a core area of 0.62 mm2 .
59 citations
TL;DR: A low-noise divider-less PLL, employing a subsampling locked loop, samples the VCO output by a digital pulse-width modulator (DPWM) to perform fractional-N operation and achieves figure-of-merit of -239.1 dB, corresponding to 266 fs rms jitter.
Abstract: A low-noise divider-less PLL, employing a subsampling locked loop, samples the VCO output by a digital pulse-width modulator (DPWM) to perform fractional-N operation. The frequency synthesizer achieves a low in-band phase noise of -112 dBc/Hz at a 2.3 GHz output frequency. The analysis for the frequency synthesizer, especially for the nonlinear characteristics of the circuits, is proposed. Fabricated in a 0.18 μm CMOS technology, the frequency synthesizer consumes 9.6 mA and achieves figure-of-merit of -239.1 dB, corresponding to 266 fs rms jitter.
56 citations
References
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IBM1
TL;DR: A 3.6-GHz digital fractional-N frequency synthesizer achieving low noise and 500-kHz bandwidth is presented, which uses a gated-ring-oscillator time-to-digital converter to achieve integrated phase noise of less than 300 fs.
Abstract: A 3.6-GHz digital fractional-N frequency synthesizer achieving low noise and 500-kHz bandwidth is presented. This architecture uses a gated-ring-oscillator time-to-digital converter (TDC) with 6-ps raw resolution and first-order shaping of its quantization noise along with digital quantization noise cancellation to achieve integrated phase noise of less than 300 fs (1 kHz to 40 MHz). The synthesizer includes two 10-bit 50-MHz passive digital-to-analog converters for digital control of the oscillator and an asynchronous frequency divider that avoids divide-value delay variation at its output. Implemented in a 0.13-mum CMOS process, the prototype occupies 0.95-mm2 active area and dissipates 39 mW for the core parts with another 8 mW for the oscillator output buffer. Measured phase noise at 3.67 GHz carrier frequency is -108 and -150 dBc/Hz at 400 kHz and 20 MHz offset, respectively.
325 citations
"A 14.2 mW 2.55-to-3 GHz Cascaded PL..." refers background in this paper
...In [6], a digital version of the quantization noise...
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TL;DR: An output-capacitorless low-dropout regulator (LDO) with a direct voltage-spike detection circuit is presented in this paper and the transient response of the LDO is significantly enhanced due to the improvement of the slew rate at the gate of the power transistor.
Abstract: An output-capacitorless low-dropout regulator (LDO) with a direct voltage-spike detection circuit is presented in this paper. The proposed voltage-spike detection is based on capacitive coupling. The detection circuit makes use of the rapid transient voltage at the LDO output to increase the bias current momentarily. Hence, the transient response of the LDO is significantly enhanced due to the improvement of the slew rate at the gate of the power transistor. The proposed voltage-spike detection circuit is applied to an output-capacitorless LDO implemented in a standard 0.35-?m CMOS technology (where VTHN ? 0.5 V and VTHP ? -0.65 V). Experimental results show that the LDO consumes 19 ?A only. It regulates the output at 0.8 V from a 1-V supply, with dropout voltage of 200 mV at the maximum output current of 66.7 mA. The voltage spike and the recovery time of the LDO with the proposed voltage-spike detection circuit are reduced to about 70 mV and 3 ?s, respectively, whereas they are more than 420 mV and 30 ?s for the LDO without the proposed detection circuit.
262 citations
"A 14.2 mW 2.55-to-3 GHz Cascaded PL..." refers methods in this paper
...To reduce the output voltage of the DAC, the folded error amplifier [15] is used....
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TL;DR: In this paper, a phase noise cancellation technique and a charge pump linearization technique are presented and demonstrated as enabling components in a wideband CMOS delta-sigma fractional-N phase-locked loop (PLL).
Abstract: A phase noise cancellation technique and a charge pump linearization technique, both of which are insensitive to component errors, are presented and demonstrated as enabling components in a wideband CMOS delta-sigma fractional-N phase-locked loop (PLL). The PLL has a loop bandwidth of 460 kHz and is capable of 1-Mb/s in- loop FSK modulation at center frequencies of 2402 + k MHz for k = 0, 1, 2, ..., 78. For each frequency, measured results indicate that the peak spot phase noise reduction achieved by the phase noise cancellation technique is 16 dB or better, and the minimum suppression of fractional spurious tones achieved by the charge pump linearization technique is 8 dB or better. With both techniques enabled, the PLL achieves a worst-case phase noise of -121 dBc/Hz at 3-MHz offsets, and a worst-case in-band noise floor of -96 dBc/Hz. The PLL circuitry consumes 34.4 mA from 1.8-2.2-V supplies. The IC is realized in a 0.18-/spl mu/m mixed-signal CMOS process, and has a die size of 2.72 mm /spl times/ 2.47 mm.
258 citations
TL;DR: In this paper, the authors proposed a new charge pump circuit with perfect current matching characteristics in a 0.25 /spl mu/m CMOS process with an error amplifier and reference current sources.
Abstract: Conventional CMOS charge pump circuits have some current mismatching characteristics. The current mismatch of the charge pump in the PLLs generates a phase offset, which increases spurs in the PLL output signals. In particular, it reduces the locking range in wide range PLLs with a dual loop scheme. A new charge pump circuit with perfect current matching characteristics is proposed. By using an error amplifier and reference current sources, one can achieve a charge pump with good current matching characteristics. It shows nearly perfect current matching characteristics over the whole VCO input range, and the amount of the reference spur is <-75 dBc in the PLL output signal. The charge pump circuit is implemented in a 0.25 /spl mu/m CMOS process.
235 citations
"A 14.2 mW 2.55-to-3 GHz Cascaded PL..." refers methods in this paper
...We use an error amplifier to adjust the PMOS bias for better current matching [16]....
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TL;DR: A multiplying delay-locked loop (MDLL) for high-speed on-chip clock generation that overcomes the drawbacks of phase-locked loops (PLLs) such as jitter accumulation, high sensitivity to supply, and substrate noise is described.
Abstract: A multiplying delay-locked loop (MDLL) for high-speed on-chip clock generation that overcomes the drawbacks of phase-locked loops (PLLs) such as jitter accumulation, high sensitivity to supply, and substrate noise is described. The MDLL design removes such drawbacks while maintaining the advantages of a PLL for multirate frequency multiplication. This design also uses a supply regulator and filter to further reduce on-chip jitter generation. The MDLL, implemented in 0.18-/spl mu/m CMOS technology, occupies a total active area of 0.05 mm/sup 2/ and has a speed range of 200 MHz to 2 GHz with selectable multiplication ratios of M=4, 5, 8, 10. The complete synthesizer, including the output clock buffers, dissipates 12 mW from a 1.8-V supply at 2.0 GHz. This MDLL architecture is used as a clock multiplier integrated on a single chip for a 72/spl times/72 STS-1 grooming switch and has a jitter of 1.73 ps (rms) and 13.1 ps (pk-pk).
222 citations
"A 14.2 mW 2.55-to-3 GHz Cascaded PL..." refers methods in this paper
...Reference injection scheme has been widely used to reduce the jitter and phase noise of a frequency synthesizer [2]–[4], [11]–[13]....
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