Proceedings ArticleDOI

# A 14 Bit Dual Channel Incremental Continuous-Time Delta Sigma Modulator for Multiplexed Data Acquisition

Kamlesh Singh
04 Jan 2016-pp 230-235

TL;DR: This work gives simple expressions for quantization and thermal noise of an incremental CTDSM that achieves a bandwidth of 6 6 kHz/channel and is used to design a two channel incrementalCTDSM.

AbstractCTDSMs operated in the incremental mode can achieve sample-by-sample conversion in a power efficient manner, while relaxing the requirements of the buffer driving the ADC. This work gives simple expressions for quantization and thermal noise of an incremental CTDSM. These are used to design a two channel incremental CTDSM that achieves a bandwidth of 6 6 kHz/channel. The ADC, designed in a 180nm CMOS process, achieves 85.1dB SNDR while consuming 55uW/channel from a 1.8 V supply.

##### Citations
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TL;DR: Various design techniques for improving the energy-efficiency of the IADCs are described and intended to serve as a starting point for the development of a new energy-efficient IADC.

10 citations

Journal ArticleDOI
TL;DR: It is shown that memoryless A/D conversion without reset can be realized using a discrete-time DSM with a signal transfer function (STF) of unity and a Nyquist -band decimation filter running at the oversampled rate.
Abstract: This paper presents new techniques to obtain sample-by-sample analog-to-digital conversion using a delta–sigma modulator (DSM) without resetting the modulator or the decimation filter. It is shown that memoryless A/D conversion without reset can be realized using a discrete-time DSM with a signal transfer function (STF) of unity and a Nyquist $M$ -band decimation filter running at the oversampled rate. It is also shown that a delta–sigma ADC preceded by a sample-and-hold at the Nyquist rate is a linear, time-invariant system at the Nyquist rate. This relaxes the constraint on the STF and allows using a multi-rate decimation filter and an equalizer at the Nyquist rate to significantly lower the power in the digital filters. Crosstalk suppression, which is limited by analog imperfections when a fixed-coefficient equalizer is used, is shown to be substantially improved using an adaptive equalizer at the Nyquist rate. A 180-nm prototype operating at 32 MHz and an OSR of 32 demonstrates two-channel operation with crosstalk below 89 dB. It consumes 18.2 mA from a 1.8-V supply, occupies 3.86 mm2 and has DR/SNR/SNDR of 84.2/82.5/80.1 dB.

8 citations

### Cites methods from "A 14 Bit Dual Channel Incremental C..."

• ...For a K th order delta-sigma modulator, the optimum decimation filter for incremental mode operation at fs/M is a K th order accumulator with transfer function 1/ ( 1 − z−1)K which is reset every M cycles [1] [6]....

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Proceedings ArticleDOI
21 Oct 2019
TL;DR: This letter presents a high-resolution continuous-time incremental delta–sigma modulator, which employs an finite impulse response (FIR) filter in its feedback, leading to an improved clock jitter robustness, relaxed linearity, and dynamic requirements of the first stage opamp.
Abstract: This letter presents a high-resolution continuous-time incremental delta–sigma modulator, which employs an finite impulse response (FIR) filter in its feedback. Due to the resetting environment of the incremental operation, the FIR digital-to-analog converter comes with added challenges to design. Thus, a differential resetting scheme between adjacent FIR taps is introduced, which allows the use of a sufficiently large number of taps in the incremental operation, leading to an improved clock jitter robustness, relaxed linearity, and dynamic requirements of the first stage opamp. A prototype is fabricated in a 180-nm CMOS process, occupying an active area of 0.175 mm2. The prototype achieves a peak SNR/SNDR of 86/83 dB, a dynamic range (DR) of 91.5 dB, and a peak spurious-free DR of 94.3 dB at a conversion rate of 200 kS/s. The power consumption is 1.27 mW from a 3-V power supply. This results in a Schreier FoM of 170.4 dB.

6 citations

Journal ArticleDOI
TL;DR: An analog‐to‐digital converter (ADC) with adaptive resolution is presented for wireless neural recording implants and achieves 8‐bit or 3‐bit resolution adaptively with 10 kHz bandwidth while the average power consumption is less than 1.89 μW from a single 1‐V power supply.
Abstract: Int J Circ Theor Appl. 2019;47:187–203. Summary In this paper, an analog‐to‐digital converter (ADC) with adaptive resolution is presented for wireless neural recording implants. The resolution of the ADC is changed according to the neural signal content, and for this purpose, a continuous‐time (CT) incremental sigma‐delta (IΣΔ) modulator is employed. The ADC digitizes the action potential (AP) and background noise (B‐noise) with 8‐bit and 3‐bit resolutions, respectively. An automatic AP detector is used to separate the APs from the B‐noise in order to select one of the two proportional resolutions. The power dissipation and output data rate of the ADC are reduced by using this technique. Analytical calculations and behavioral simulation results are provided to evaluate the performance of the proposed ADC. To further confirm its efficiency, the circuit‐level implementation of the CT IΣΔ ADC is presented in Taiwan Semiconductor Manufacturing Company (TSMC) 90‐nm complementary metal‐oxide semiconductor (CMOS) process. According to the simulation results, the proposed ADC achieves 8‐bit or 3‐bit resolution adaptively with 10 kHz bandwidth while the average power consumption is less than 1.89 μW from a single 1‐V power supply.

5 citations

### Cites background from "A 14 Bit Dual Channel Incremental C..."

• ...Although most IΣΔ ADCs have been implemented as discrete‐time (DT) circuits, continuous‐time (CT) IΣΔ ADCs have been considered in recent years.(6,9) In CT ΣΔ ADCs, the required gain‐bandwidth (GBW) of the operational amplifiers is less than the DT counterpart resulting in lower‐power consumption....

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Journal ArticleDOI

TL;DR: The detector employs a 3T pixel with a voltage-controlled storage capacitor to achieve both a low dark random noise (RN) and a large well capacity, and the pixel outputs are read out by column-parallel continuous-time (CT) incremental delta–sigma analog-to-digital converters (ADCs).
Abstract: This article presents a 5.2-Mpixel, 12-in wafer-scale CMOS X-ray detector that consists of lithographically stitched 169 sub-chips. The detector employs a 3T pixel with a voltage-controlled storage capacitor to achieve both a low dark random noise (RN) and a large well capacity, and the pixel outputs are read out by column-parallel continuous-time (CT) incremental delta–sigma ( $\Delta \Sigma$ ) analog-to-digital converters (ADCs). The use of a CT incremental $\Delta \Sigma$ ADC enables high resolution and low energy consumption while securing uniformity and robustness over the 12-in wafer. This work is fabricated in a 1P4M 65-nm CMOS technology. The 16-bit ADC implemented within a 45- $\mu \text{m}$ pitch achieves a differential nonlinearity (DNL) of +0.79/−0.65 LSB, an integral nonlinearity (INL) of +6.85/−6.15 LSB, and a peak signal-to-noise ratio (SNR) of 88.5 dB with a conversion time of $12.6~\mu \text{s}$ . This detector achieves a CFPN of $181~\mu \text {V}_{\text {rms}}$ , a dark RN of $267~\mu \text {V}_{\text {rms}}$ , and a DR of 88.4 dB while consuming 3.9 W at 30 frames/s. Compared with the state of the arts, this work achieves $3\times$ larger spatial resolution, $1.8\times$ higher pixel rate, $1.9\times$ higher energy-efficiency, and 17 dB higher DR, simultaneously.

3 citations

##### References
More filters
Journal ArticleDOI
, J. Silva1
TL;DR: It is shown how speed, resolution, and A/D complexity can be optimized for a given design, and how with some special digital filters improved speed/resolution ratio can be achieved.
Abstract: Analog-Digital (A/D) converters used in instrumentation and measurements often require high absolute accuracy, including very high linearity and negligible dc offset. The realization of high-resolution Nyquist-rate converters becomes very expensive when the resolution exceeds 16 bits. The conventional delta-sigma (/spl Delta//spl Sigma/) structures used in telecommunication and audio applications usually cannot satisfy the requirements of high absolute accuracy and very small offset. The incremental (or integrating) converter provides a solution for such measurement applications, as it has most advantages of the /spl Delta//spl Sigma/ converter, yet is capable of offset-free and accurate conversion. In this paper, theoretical and practical aspects of higher order incremental converters are discussed. The operating principles, topologies, specialized digital filter design methods, and circuit level issues are all addressed. It is shown how speed, resolution, and A/D complexity can be optimized for a given design, and how with some special digital filters improved speed/resolution ratio can be achieved. The theoretical results are verified by showing design examples and simulation results.

254 citations

Journal ArticleDOI

TL;DR: A low-power 22-bit incremental ADC, including an on-chip digital filter and a low-noise/low-drift oscillator, realized in a 0.6-mum CMOS process, incorporates a novel offset-cancellation scheme based on fractal sequences, a novel high-accuracy gain control circuit, and a novel reduced-complexity realization for the on- chip sinc filter.
Abstract: This paper describes a low-power 22-bit incremental ADC, including an on-chip digital filter and a low-noise/low-drift oscillator, realized in a 0.6-mum CMOS process. It incorporates a novel offset-cancellation scheme based on fractal sequences, a novel high-accuracy gain control circuit, and a novel reduced-complexity realization for the on-chip sinc filter. The measured output noise was 0.25 ppm (2.5 muVRMS), the DC offset 2 muV, the gain error 2 ppm, and the INL 4 ppm. The chip operates with a single 2.7-5 V supply, and draws only 120 muA current during conversion

124 citations

Journal ArticleDOI
TL;DR: The “assisted opamp” integrator is introduced, which is a way of achieving low distortion operation with low power consumption and circuit implementations of the technique for single-bit modulators using NRZ and switched-capacitor-resistor feedback DACs are presented.
Abstract: The opamp in the first integrator of a high resolution single-bit continuous-time modulator has stringent slew rate requirements, which increases power dissipation. We introduce the “assisted opamp” integrator, which is a way of achieving low distortion operation with low power consumption. We present circuit implementations of our technique for single-bit modulators using NRZ and switched-capacitor-resistor (SCR) feedback DACs. Audio modulators designed in a 0.18 μm CMOS technology are used as vehicles to demonstrate the effectiveness of our techniques. The modulator with an NRZ DAC achieves a dynamic range of 92.5 dB in a 24 kHz bandwidth and dissipates 110 μW from a 1.8 V supply. A second design, which employs an SCR-DAC, achieves a dynamic range of 91.5 dB and dissipates 122 μW. The figures of merit (FOM) of these modulators, 175.9 dB and 174.4 dB respectively, are comparable with those of state-of-the-art multibit designs.

78 citations

### "A 14 Bit Dual Channel Incremental C..." refers methods in this paper

• ...The linearity of the first integrator of the CTΔΣM was enhanced using opamp assistance [3]....

[...]

• ...The assistant transconductor that senses the input voltage and injects an appropriate current into the output of the first OTA is a class-AB design, similar to the one used in [3]....

[...]

Journal Article
TL;DR: In this article, a 3 rd order single-loop continuous-time incremental sigma-delta analogue-to-digital con- verter (ADC) for time-multiplexed signals is proposed.
Abstract: This paper proposes a 3 rd order single-loop continuous-time incremental sigma-delta analogue-to-digital con- verter (ADC) for time-multiplexed signals. Incremental sigma- delta modulation is used to address medium to high resolution requirements of multi-channel applications, while a 3 rd order continuous-time implementation is investigated as an alternative for low-power solutions. A prototype of the proposed modulator, running at 320 kHz, has been fabricated in a 0.15-µm CMOS technology, while the synchronization circuitry to allow incre- mental operation was built on-board. Measurement results show that the ADC achieves 65.3 dB peak SNR, 64 dB peak SNDR and 68.2 dB dynamic range over a 2 kHz bandwidth. The modulator's power dissipation is 96 µW from a 1.6 V power supply. This translates into the best figure-of-merit when compared to recently published continuous-time alternatives, while being competitive with respect to state-of-the-art discrete-time counterparts. Index Terms—A/D conversion, incremental ADC, continuous-time.

55 citations

Journal ArticleDOI
TL;DR: This paper proposes a 3rd order single-loop continuous-time incremental sigma-delta analogue-to-digital converter (ADC) for time-multiplexed signals, being competitive with respect to state-of-the-art discrete-time counterparts.
Abstract: This paper proposes a 3rd order single-loop continuous-time incremental sigma-delta analogue-to-digital converter (ADC) for time-multiplexed signals. Incremental sigma-delta modulation is used to address medium to high resolution requirements of multi-channel applications, while a 3rd order continuous-time implementation is investigated as an alternative for low-power solutions. A prototype of the proposed modulator, running at 320 kHz, has been fabricated in a 0.15-μm CMOS technology, while the synchronization circuitry to allow incremental operation was built on-board. Measurement results show that the ADC achieves 65.3 dB peak SNR, 64 dB peak SNDR and 68.2 dB dynamic range over a 2 kHz bandwidth. The modulator's power dissipation is 96 μW from a 1.6 V power supply. This translates into the best figure-of-merit when compared to recently published continuous-time alternatives, while being competitive with respect to state-of-the-art discrete-time counterparts.

41 citations