A 14 Bit Dual Channel Incremental Continuous-Time Delta Sigma Modulator for Multiplexed Data Acquisition
TL;DR: This work gives simple expressions for quantization and thermal noise of an incremental CTDSM that achieves a bandwidth of 6 6 kHz/channel and is used to design a two channel incrementalCTDSM.
Abstract: CTDSMs operated in the incremental mode can achieve sample-by-sample conversion in a power efficient manner, while relaxing the requirements of the buffer driving the ADC. This work gives simple expressions for quantization and thermal noise of an incremental CTDSM. These are used to design a two channel incremental CTDSM that achieves a bandwidth of 6 6 kHz/channel. The ADC, designed in a 180nm CMOS process, achieves 85.1dB SNDR while consuming 55uW/channel from a 1.8 V supply.
Cites methods from "A 14 Bit Dual Channel Incremental C..."
...For a K th order delta-sigma modulator, the optimum decimation filter for incremental mode operation at fs/M is a K th order accumulator with transfer function 1/ ( 1 − z−1)K which is reset every M cycles  ....
Cites background from "A 14 Bit Dual Channel Incremental C..."
...Although most IΣΔ ADCs have been implemented as discrete‐time (DT) circuits, continuous‐time (CT) IΣΔ ADCs have been considered in recent years.(6,9) In CT ΣΔ ADCs, the required gain‐bandwidth (GBW) of the operational amplifiers is less than the DT counterpart resulting in lower‐power consumption....
"A 14 Bit Dual Channel Incremental C..." refers methods in this paper
...The linearity of the first integrator of the CTΔΣM was enhanced using opamp assistance ....
...The assistant transconductor that senses the input voltage and injects an appropriate current into the output of the first OTA is a class-AB design, similar to the one used in ....
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