Proceedings ArticleDOI
A 14 Bit Dual Channel Incremental Continuous-Time Delta Sigma Modulator for Multiplexed Data Acquisition
Kamlesh Singh,Shanthi Pavan +1 more
- pp 230-235
Reads0
Chats0
TLDR
This work gives simple expressions for quantization and thermal noise of an incremental CTDSM that achieves a bandwidth of 6 6 kHz/channel and is used to design a two channel incrementalCTDSM.Abstract:
CTDSMs operated in the incremental mode can achieve sample-by-sample conversion in a power efficient manner, while relaxing the requirements of the buffer driving the ADC. This work gives simple expressions for quantization and thermal noise of an incremental CTDSM. These are used to design a two channel incremental CTDSM that achieves a bandwidth of 6 6 kHz/channel. The ADC, designed in a 180nm CMOS process, achieves 85.1dB SNDR while consuming 55uW/channel from a 1.8 V supply.read more
Citations
More filters
Journal ArticleDOI
Incremental Delta-Sigma ADCs: A Tutorial Review
TL;DR: Various design techniques for improving the energy-efficiency of the IADCs are described and intended to serve as a starting point for the development of a new energy-efficient IADC.
Journal ArticleDOI
Reset-Free Memoryless Delta–Sigma Analog-to-Digital Conversion
TL;DR: It is shown that memoryless A/D conversion without reset can be realized using a discrete-time DSM with a signal transfer function (STF) of unity and a Nyquist -band decimation filter running at the oversampled rate.
Journal ArticleDOI
A 5.2-Mpixel 88.4-dB DR 12-in CMOS X-Ray Detector With 16-bit Column-Parallel Continuous-Time Incremental ΔΣ ADCs
TL;DR: The detector employs a 3T pixel with a voltage-controlled storage capacitor to achieve both a low dark random noise (RN) and a large well capacity, and the pixel outputs are read out by column-parallel continuous-time (CT) incremental delta–sigma analog-to-digital converters (ADCs).
Journal ArticleDOI
An adaptive continuous-time incremental Σ∆ ADC for neural recording implants
Saeid Barati,Mohammad Yavari +1 more
TL;DR: An analog‐to‐digital converter (ADC) with adaptive resolution is presented for wireless neural recording implants and achieves 8‐bit or 3‐bit resolution adaptively with 10 kHz bandwidth while the average power consumption is less than 1.89 μW from a single 1‐V power supply.
Proceedings ArticleDOI
A 94.3-dB SFDR, 91.5-dB DR, and 200-kS/s CT Incremental Delta–Sigma Modulator With Differentially Reset FIR Feedback
TL;DR: This letter presents a high-resolution continuous-time incremental delta–sigma modulator, which employs an finite impulse response (FIR) filter in its feedback, leading to an improved clock jitter robustness, relaxed linearity, and dynamic requirements of the first stage opamp.
References
More filters
Journal ArticleDOI
Theory and applications of incremental /spl Delta//spl Sigma/ converters
TL;DR: It is shown how speed, resolution, and A/D complexity can be optimized for a given design, and how with some special digital filters improved speed/resolution ratio can be achieved.
Journal ArticleDOI
A low-power 22-bit incremental ADC
Vincent Quiquempoix,Philippe Deval,Alexandre Barreto,Gabriele Bellini,János Márkus,Jose Barreiro Silva,Gabor C. Temes +6 more
TL;DR: A low-power 22-bit incremental ADC, including an on-chip digital filter and a low-noise/low-drift oscillator, realized in a 0.6-mum CMOS process, incorporates a novel offset-cancellation scheme based on fractal sequences, a novel high-accuracy gain control circuit, and a novel reduced-complexity realization for the on- chip sinc filter.
Journal ArticleDOI
Power Reduction in Continuous-Time Delta-Sigma Modulators Using the Assisted Opamp Technique
Shanthi Pavan,Prabu Sankar +1 more
TL;DR: The “assisted opamp” integrator is introduced, which is a way of achieving low distortion operation with low power consumption and circuit implementations of the technique for single-bit modulators using NRZ and switched-capacitor-resistor feedback DACs are presented.
Journal Article
A Low-Power CT Incremental 3rd Order ΣΔ ADC for Biosensor Applications.
TL;DR: In this article, a 3 rd order single-loop continuous-time incremental sigma-delta analogue-to-digital con- verter (ADC) for time-multiplexed signals is proposed.
Journal ArticleDOI
A Low-Power CT Incremental 3rd Order /spl Sigma//spl Delta/ ADC for Biosensor Applications
TL;DR: This paper proposes a 3rd order single-loop continuous-time incremental sigma-delta analogue-to-digital converter (ADC) for time-multiplexed signals, being competitive with respect to state-of-the-art discrete-time counterparts.
Related Papers (5)
A 14-bit delta-sigma ADC with 8/spl times/ OSR and 4-MHz conversion bandwidth in a 0.18-/spl mu/m CMOS process
Ruoxin Jiang,Terri S. Fiez +1 more