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Proceedings ArticleDOI

A 14 Bit Dual Channel Incremental Continuous-Time Delta Sigma Modulator for Multiplexed Data Acquisition

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TLDR
This work gives simple expressions for quantization and thermal noise of an incremental CTDSM that achieves a bandwidth of 6 6 kHz/channel and is used to design a two channel incrementalCTDSM.
Abstract
CTDSMs operated in the incremental mode can achieve sample-by-sample conversion in a power efficient manner, while relaxing the requirements of the buffer driving the ADC. This work gives simple expressions for quantization and thermal noise of an incremental CTDSM. These are used to design a two channel incremental CTDSM that achieves a bandwidth of 6 6 kHz/channel. The ADC, designed in a 180nm CMOS process, achieves 85.1dB SNDR while consuming 55uW/channel from a 1.8 V supply.

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Citations
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Journal ArticleDOI

Incremental Delta-Sigma ADCs: A Tutorial Review

TL;DR: Various design techniques for improving the energy-efficiency of the IADCs are described and intended to serve as a starting point for the development of a new energy-efficient IADC.
Journal ArticleDOI

Reset-Free Memoryless Delta–Sigma Analog-to-Digital Conversion

TL;DR: It is shown that memoryless A/D conversion without reset can be realized using a discrete-time DSM with a signal transfer function (STF) of unity and a Nyquist -band decimation filter running at the oversampled rate.
Journal ArticleDOI

A 5.2-Mpixel 88.4-dB DR 12-in CMOS X-Ray Detector With 16-bit Column-Parallel Continuous-Time Incremental ΔΣ ADCs

TL;DR: The detector employs a 3T pixel with a voltage-controlled storage capacitor to achieve both a low dark random noise (RN) and a large well capacity, and the pixel outputs are read out by column-parallel continuous-time (CT) incremental delta–sigma analog-to-digital converters (ADCs).
Journal ArticleDOI

An adaptive continuous-time incremental Σ∆ ADC for neural recording implants

TL;DR: An analog‐to‐digital converter (ADC) with adaptive resolution is presented for wireless neural recording implants and achieves 8‐bit or 3‐bit resolution adaptively with 10 kHz bandwidth while the average power consumption is less than 1.89 μW from a single 1‐V power supply.
Proceedings ArticleDOI

A 94.3-dB SFDR, 91.5-dB DR, and 200-kS/s CT Incremental Delta–Sigma Modulator With Differentially Reset FIR Feedback

TL;DR: This letter presents a high-resolution continuous-time incremental delta–sigma modulator, which employs an finite impulse response (FIR) filter in its feedback, leading to an improved clock jitter robustness, relaxed linearity, and dynamic requirements of the first stage opamp.
References
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Proceedings ArticleDOI

A 12-bit 7 µW/channel 1 kHz/channel incremental ADC for biosensor interface circuits

TL;DR: A two-channel micro-power incremental ADC, designed for biosensor interface circuits, is reported, which uses a noise-coupled multi-bit delta-sigma loop, integrated with a novel digital decimation filter operating in near-threshold.
Proceedings ArticleDOI

A 105-dB SNDR, 10 kSps multi-level second-order incremental converter with smart-DEM consuming 280 µW and 3.3-V supply

TL;DR: This paper presents a second-order 3-bit incremental converter, which uses a novel Smart-DEM algorithm for mismatch compensation of multi-level DAC unity elements, which achieves more than 17-bit resolution over a 5-kHz bandwidth using 256 clock periods.
Proceedings ArticleDOI

A frequency-scalable 15-bit incremental ADC for low power sensor applications

TL;DR: A 15-bit low-power incremental ADC is designed for sensor applications and designed to be frequency-scalable by 1000 times from 1.67S/S to 1.
Proceedings ArticleDOI

82 dB SNDR 20-channel incremental ADC with optimal decimation filter and digital correction

TL;DR: A third-order multi-channel incremental ADC with a 5-level quantizer is presented which minimizes the weighted sum of the thermal and quantization output noises and obtained a signal-to-noise-and-distortion ratio of 81.5 dB.
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