A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access
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Cites methods from "A 14 nm 1.1 Mb Embedded DRAM Macro ..."
...SRAM buffers within each cluster and the eDRAM memory are modeled using CACTI7 [49] using 14nm eDRAM parameters from [50]....
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Cites background from "A 14 nm 1.1 Mb Embedded DRAM Macro ..."
...Embedding dynamic-random access memory [1], [2], built with...
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Additional excerpts
...With these advantages, high-performance server processors [9,10] and deep neural network (DNN) hardware accelerators [11,12] have adopted eDRAM as their on-chip memory....
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References
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"A 14 nm 1.1 Mb Embedded DRAM Macro ..." refers methods in this paper
...IBM introduced trench capacitor eDRAM into its high performance microprocessors beginning with 45nm and Power 7 [1] to provide a higher density cache without chip crossings....
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137 citations
"A 14 nm 1.1 Mb Embedded DRAM Macro ..." refers methods in this paper
...1(a), utilizes Replacement Metal Gate (RMG) SOI FinFET devices, resulting in a 33% shrink from the 22 nm bit cell [16], [17]....
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...The pass transistor/access device of the cell is a 3.5 nm thick oxide, fully depleted (FD) FinFET with an undoped channel....
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...This 22 nm design style has been successfully migrated into a 14 nm FinFET eDRAM [20] learning vehicle, complete with an ABIST engine, word-line charge pumps (VPP & VWL), and pad-cage interface circuitry as a system prototype....
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...Hence, FD SOI FinFETs can achieve high write back current without increasing the LBL capacitance, which is a key advantage to previous eDRAM technologies employing planar pass transistors....
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...By nature, SOI fully depleted FinFET devices, have low overall junction capacitance as the only junctions created in the SOI are in the horizontal plane of the device, i.e., between the body of the device and diffusion....
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