A 198.9GHz-to-201.0GHz injection-locked frequency divider in 65nm CMOS
16 Jun 2010-pp 49-50
TL;DR: In this paper, an injection-locked frequency divider (ILFD) is realized in 65nm CMOS technology for G-band (140 to 220GHz) applications, which consumes 8.8mW from a 1.1V supply.
Abstract: An injection-locked frequency divider (ILFD) is realized in 65nm CMOS technology for G-band (140 to 220GHz) applications. Its core area is 0.2×0.16mm2. This ILFD consumes 8.8mW from a 1.1V supply excluding the buffers. Due to the limited output power of the source module (i.e., frequency multiplier), the measured locking range of this ILFD is from 198.9GHz to 201.0GHz.
Citations
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TL;DR: To enable CMOS prescaler(s) for submillimeter-wave radio-frequency synthesis, this work presents a new dynamic frequency divider topology according to a time-interleaved dual-injection locking scheme that has demonstrated ultra high operation speeds and ultra wide locking range.
Abstract: To enable CMOS prescaler(s) for submillimeter-wave radio-frequency synthesis, we present a new dynamic frequency divider topology according to a time-interleaved dual-injection locking scheme. Consequently, the prototype prescalers implemented with 65-nm CMOS technology have demonstrated ultra high operation speeds up to 208 GHz, with ultra wide locking range up to 37 GHz, with 2.5-mW power consumption. The achieved performance figure of merit (FOM) [i.e., (speed X range)/power in GHz2/mW] is roughly an order of magnitude higher than that of the state of the art.
12 citations
Cites background from "A 198.9GHz-to-201.0GHz injection-lo..."
...For example, [3] demonstrated a 14% locking arrange with lower than 100-GHz dividing frequency, whereas [4] and [5] achieved higher dividing frequencies of 120 and 130 GHz, respectively, with a much smaller locking range of 7%....
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TL;DR: Four divide-by-3 injection-locked frequency dividers (ILFDs) are fabricated in 40-nm CMOS technology using a second-harmonic peaking technique and the distributed inductor technique to enhance the operation frequency and the locking range.
Abstract: Four divide-by-3 injection-locked frequency dividers (ILFDs) are fabricated in 40-nm CMOS technology. A second-harmonic peaking technique is used to enhance the locking range. The distributed inductor technique is used to enhance the operation frequency and the locking range. The locking range and design considerations of the proposed ILFDs are discussed. The largest measured locking range among four ILFDs is 236.6~245.2 GHz. The highest operation frequency is over 280 GHz. These ILFDs consume 2.97~3.96 mW from a supply of 1.1 V excluding output buffers.
9 citations
TL;DR: The frequency enhancement analysis and design considerations for the both ILFDs are given and the effects of vias and interconnections on the inductance and quality factor are discussed.
Abstract: Two high-frequency CMOS injection-locked frequency dividers (ILFDs) are realized by π-type LC networks. The frequency enhancement analysis and design considerations for the both ILFDs are given. The effects of vias and interconnections on the inductance and quality factor are also discussed. Both ILFDs have been fabricated in 65 nm CMOS process. The measured locking ranges of these two ILFDs are 182.7-185.7 GHz and 192.4-194.06 GHz, respectively.
9 citations
TL;DR: In this paper, a 300 GHz divide-by-2 ILFD is fabricated in 40 nm CMOS technology, which adopts π-type LC networks with a negative coupling technique to enhance the oscillation frequency.
Abstract: A 300 GHz divide-by-2 ILFD is fabricated in 40 nm CMOS technology. This ILFD adopts π-type LC networks with a negative coupling technique to enhance the oscillation frequency. The oscillation frequency and the locking range of the proposed ILFD are analyzed. The measured locking range is 297.08-306.64 GHz. The ILFD consumes 9.18 mW under a standard supply of 0.9 V excluding output buffers.
7 citations
Cites background from "A 198.9GHz-to-201.0GHz injection-lo..."
...In [4], two common-source amplifiers are added to oscillate at the second pole....
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01 Jan 2012
TL;DR: In this article, a single-ended divide-by-two injection-locked frequency divider with inductive feedback was presented, with a measured locking range of 126.9-141.5 GHz (14.7 GHz) with bias adjustment.
Abstract: In this work, a single-ended divide-by-2 injection locked frequency divider with inductive feedback is presented. The frequency divider, fabricated in a commercial 0.18 μm SiGe HBT technology, showed a measured locking range of 126.9–141.5 GHz (14.7 GHz) and an operating range of 126.9–150.0 GHz (23.1 GHz) with bias adjustment. The DC power consumption of the ILFD core was 6.9 mW and that of the output buffer was 13.5 mW.
7 citations
References
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TL;DR: A 40-Gb/s transimpedance amplifier (TIA) is realized in 0.18-mum CMOS technology with bandwidth enhancement technique, pi-type inductor peaking (PIP), to achieve a bandwidth enhancement ratio (BWER) of 3.31.
Abstract: A 40-Gb/s transimpedance amplifier (TIA) is realized in 0.18-mum CMOS technology. From the measured S-parameters, a transimpedance gain of 51 dBOmega and a 3-dB bandwidth up to 30.5 GHz were observed. A bandwidth enhancement technique, pi-type inductor peaking (PIP), is proposed to achieve a bandwidth enhancement ratio (BWER) of 3.31. In addition, the PIP topology used at the input stage decreases the noise current as the operation frequency increases. Under a 1.8 V supply voltage, the TIA consumes 60.1 mW with a chip area of 1.17 X 0.46 mm2. The proposed CMOS TIA presents a gain-bandwidth product per DC power figure of merit (GBP/Pde) of 180.1 GHzOmega/mW.
112 citations
TL;DR: An inductive feedback technique increases the speed of resonant circuits by 62%, allowing operation near the fT of transistors, leading to a fundamental oscillator operating at 128 GHz with a power dissipation of 9 mW and a phase noise of -105 dBc/Hz at 10-MHz offset.
Abstract: An inductive feedback technique increases the speed of resonant circuits by 62%, allowing operation near the fT of transistors. The technique leads to a fundamental oscillator operating at 128 GHz with a power dissipation of 9 mW and a phase noise of -105 dBc/Hz at 10-MHz offset. A divide-by-two circuit based on the idea and incorporating a sampling mixer achieves a maximum speed of 125 GHz while consuming 10.5 mW. The prototypes have been fabricated in 90-nm CMOS technology.
57 citations
01 Jan 2004
TL;DR: In this article, a static, current mode logic (CML) frequency divider to clock frequencies exceeding 150GHz is reported, operating in a highly scaled 0.4/spl mu/m InP/InGaAs/InP DHBT technology, dissipating only 45mW per latch.
Abstract: Operation of a static, current mode logic (CML) frequency divider to clock frequencies exceeding 150GHz is reported. The divide-by-8 circuit described here has been realized in a highly scaled 0.4/spl mu/m InP/InGaAs/InP DHBT technology, dissipates only 45mW per latch, and achieves this using purely resistive loads. Thermal limitations in device performance are observed to play a key role, demonstrating the need for aggressive heat management in high speed technologies. On a full thickness wafer in a 27/spl deg/C ambient, the maximum operating frequency of the divider was 143.6GHz; this range extended to 151.2GHz when an air flow at -30/spl deg/C was established across the wafer.
27 citations
"A 198.9GHz-to-201.0GHz injection-lo..." refers background or methods in this paper
...The performance summary of the proposed ILFD and comparison with [1-5] are given in Table I....
[...]
...Table I Performance summary and comparison [1] [2] [3] [4] [5] This Work Technology 0....
[...]
...There are several G-band frequency dividers [1-3] by using DHBT processes....
[...]
01 Jan 2003
TL;DR: In this paper, an ultra-high-speed frequency divider IC using InP/InGaAs DHBTs was developed using a clocked-inverter feed-forward toggle flip-flop.
Abstract: An ultrahigh-speed frequency divider IC using InP/InGaAs DHBTs was developed A clocked-inverter feed-forward toggle flip-flop is employed in the IC The maximum measurement frequency of the IC is 150 GHz To the best of our knowledge, the operating frequency is fastest frequency divider so far reported
26 citations
"A 198.9GHz-to-201.0GHz injection-lo..." refers background or methods in this paper
...The performance summary of the proposed ILFD and comparison with [1-5] are given in Table I....
[...]
...Table I Performance summary and comparison [1] [2] [3] [4] [5] This Work Technology 0....
[...]
...There are several G-band frequency dividers [1-3] by using DHBT processes....
[...]
11 Jun 2006
TL;DR: In this paper, a new topology for a very high speed regenerative divider by four is proposed, which uses a double mixer to directly divide the input frequency by four, and operates in a frequency range from 80 GHz to 160 GHz while consuming a 650 mW from a 5.5 V supply.
Abstract: A new topology for a very high speed regenerative divider by four is proposed. The circuit uses a double mixer to directly divide the input frequency by four. A validation chip has been developed in a 225 GHz fT SiGe bipolar technology. The circuit operates in a frequency range from 80 GHz to 160 GHz while consuming a 650 mW from a ?5.5 V supply.
16 citations
"A 198.9GHz-to-201.0GHz injection-lo..." refers background or methods in this paper
...The performance summary of the proposed ILFD and comparison with [1-5] are given in Table I....
[...]
...Table I Performance summary and comparison [1] [2] [3] [4] [5] This Work Technology 0....
[...]
...There are several G-band frequency dividers [1-3] by using DHBT processes....
[...]