A 2.2dB NF, 4.9–6GHz direct conversion multi-standard RF receiver front-end in 90nm CMOS
15 Jul 2008-pp 617-620
TL;DR: In this article, a multi-standard direct conversion receiver achieves 2.2 dB NF at 6 GHz with a 15 kHz flicker noise corner, and power dissipation is 56 mW from 1.3 V and active die area is less than 1.2 mm2.
Abstract: A multi-standard direct conversion receiver achieves 2.2 dB NF at 6 GHz with a 15 kHz flicker noise corner. 1 dB RF bandwidth is 4.9-6 GHz, power dissipation is 56 mW from 1.3 V and active die area is less than 1.2 mm2, including the input matching network. Inband P1 dB and IIP3 at maximum gain (39 dB) are -30 dBm and -18 dBm, respectively, and three gain steps of 6 dB are provided. DC offset from self mixing is less than 10 mV.
Citations
More filters
TL;DR: With a thorough and accurate mathematical analysis it is shown how to design this mixer and its current buffer, and how to size components to get the best linearity, conversion gain and noise figure while alleviating the IQ cross-talk problem.
Abstract: Properties of the current-driven passive mixer are explored to maximize its performance in a zero-IF receiver. Since there is no reverse isolation between the RF and baseband sides of the mixer, the mixer reflects the baseband impedance to the RF and vice versa through simple frequency shifting. It is also shown that in an IQ down-conversion system the lack of reverse isolation causes a mutual interaction between the two quadrature mixers, which results in different high- and low-side conversion gains, and unexpected IIP2 and IIP3 values. With a thorough and accurate mathematical analysis it is shown how to design this mixer and its current buffer, and how to size components to get the best linearity, conversion gain and noise figure while alleviating the IQ cross-talk problem.
187 citations
Cites methods from "A 2.2dB NF, 4.9–6GHz direct convers..."
...rent-driven passive mixer has been used in numerous receivers [10]–[15]....
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TL;DR: A broadband CMOS direct-conversion receiver with on-chip frequency divider has been integrated in a 0.13- μm CMOS process and employs a broadband common-gate LNTA with dual feedback to improve both gain and noise figure (NF) without breaking the fixed relationship between input impedance, transconductance gain, and load impedance.
Abstract: A broadband CMOS direct-conversion receiver with on-chip frequency divider has been integrated in a 0.13- μm CMOS process. The key feature of the proposed receiver front-end is a single low-noise transconductance amplifier (LNTA) driving a current-mode passive mixer terminated by a low-input-impedance transimpedance amplifier (TIA). The receiver chain has improved robustness to out-of-band interference and outstanding linearity. We employ a broadband common-gate (CG) LNTA with dual feedback to improve both gain and noise figure (NF) without breaking the fixed relationship between input impedance, transconductance gain, and load impedance. A LNTA load impedance boosting technique suppresses noise-amplification due to TIA, commonly found in passive mixers. The core circuit (RF and baseband signal path) consumes only 13 mW, and the prototype receiver achieves >22.4-dB conversion gain, dB NF, and ≥ -1.5 dBm IIP3 from 1.4 to 5.2 GHz. Maximum conversion gain of 24.3 dB and minimum NF of 6.5 dB are achieved at 1.4 and 2 GHz, respectively. The chip active area is 1.1 mm 2 with the entire RF signal path operated from a 1.2-V supply. The LO portion is biased from a 1.5-V supply.
62 citations
Cites background from "A 2.2dB NF, 4.9–6GHz direct convers..."
...Thus, the RF transconductance of the receiver front-end should be large, and this requirement has been met in previous works [4], [6], [7] employing inductor-degenerated LNAs....
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...While a narrowband receiver can null this noise effect employing an LC tank load for LNTA [4], [6], [7], a broadband receiver suffers degraded NF....
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...Inductor-degenerated LNTA can be adopted in narrow-band implementations [4], [6], [7], where large transconductance ( 20 mS) with 50- input impedance synthesis is allowed....
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01 Jan 2012
TL;DR: In this article, the authors present a literature review on LNA design and present performance trade-offs in LNA's load load and noise figure, as well as an overview of the LNA architecture and parameters.
Abstract: .......................................................................................................................... I Acknowledgement ......................................................................................................... IV TABLE OF CONTENTS ............................................................................................... V LIST OF FIGURES .................................................................................................... VIII LIST OF TABLES ........................................................................................................ XI 1. Chapter 1: Introduction ............................................................................................ 1 1.1 Motivation......................................................................................................... 1 1.2 Objective and Major contributions..................................................................... 2 1.3 Thesis organization ........................................................................................... 4 2. Chapter 2: Literature review on LNA design ............................................................ 5 2.1 Receiver architectures ....................................................................................... 5 2.1.1 Heterodyne Receiver .................................................................................. 5 2.1.2 Homodyne Receiver (Direct conversion receiver)....................................... 7 2.2 Design parameters ............................................................................................. 9 2.2.1 Sensitivity .................................................................................................. 9 2.2.2 Noise figure ............................................................................................... 9 2.2.3 Harmonic distortion and Intermodulation ................................................. 12 2.2.4 Dynamic Range ........................................................................................ 17 2.2.5 S-Parameters ............................................................................................ 18 2.3 Introduction to LNA ........................................................................................ 20 2.3.1 Performance trade-offs in LNA design ..................................................... 22 2.3.2 Input Architecture .................................................................................... 29 2.3.3 Tuning techniques of LNA's Load ............................................................ 40
13 citations
07 Jun 2009
TL;DR: A fully integrated transmit chain for 802.11a band with on-chip power amplifier and on- chip balun matching network in 45nm standard digital CMOS process demonstrates saturated power of +23dBm.
Abstract: A fully integrated transmit chain for 802.11a band with on-chip power amplifier and on-chip balun matching network in 45nm standard digital CMOS process demonstrates saturated power of +23dBm. The average efficiency is +5% and peak efficiency is +15%. A standalone class AB CMOS power amplifier with on-chip BALUN matching network was also produced and detailed characterization data is presented. Using digital predistortion, an EVM of −28dB is achieved at 19dBm for 5GHz band and 2.5GHz band for standalone Power Amplifier.
13 citations
Additional excerpts
...Transmitter Chain 978-1-4244-3376-6/978-1-4244-3378-0/09/$25.00 © 2009 IEEE 2009 IEEE Radio Frequency Integrated Circuits Symposium 273...
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05 Jun 2011
TL;DR: In this article, a baseband transimpedance amplifier for coexisting radio receivers is presented, which exploits active feedback to improve out-of-band large-signal attenuation, minimizing in-band distortion due to close-in blockers.
Abstract: A baseband transimpedance amplifier for coexisting radio receivers is presented. It exploits active feedback to improve out-of-band large-signal attenuation, minimizing in-band distortion due to close-in blockers. A fully-differential prototype of the proposed solution has been designed and implemented in 45nm CMOS. Experimental results show that it can handle linearly single tones of ±10mA, withstanding blocking currents of ±9mA at 50MHz and beyond before reaching P1dB in a 10MHz bandwidth. The fabricated device occupies 0.25mm2, largely MOM finger capacitors, and draws 17mA from a 2.5V supply.
10 citations
Cites background from "A 2.2dB NF, 4.9–6GHz direct convers..."
...It exploits active feedback to improve out-of-band large-signal attenuation, minimizing in-band distortion due to close-in blockers....
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References
More filters
TL;DR: A direct conversion 802.11a receiver front-end including a synthesizer with quadrature VCO has been integrated in a 0.13-/spl mu/m CMOS process, which is a current driven passive mixer with a low impedance load that achieves a low 1/f noise corner and an high I-Q accuracy quadratures VCO.
Abstract: A direct conversion 802.11a receiver front-end including a synthesizer with quadrature VCO has been integrated in a 0.13-/spl mu/m CMOS process. The chip has an active area of 1.8 mm/sup 2/ with the entire RF portion operated from 1.2 V and the low frequency portion operated from 2.5 V. Its key features are a current driven passive mixer with a low impedance load that achieves a low 1/f noise corner and an high I-Q accuracy quadrature VCO. Measured noise figure is 3.5 dB with an 1/f noise corner of 200 kHz, and an IIP3 of -2 dBm. The synthesizer DSB phase noise integrated over a 10 MHz band is less than -36 dBc while its I-Q phase unbalance is below 1 degree.
143 citations
01 Feb 2008
TL;DR: A reconfigurable power-adaptive DT DeltaSigma ADC for intelligent 802.11n/WiMAX receivers (20 to 2.5MHz per I/Q) is presented and Spectrum sensing and reconfigurability are accomplished without compromising ADC performance.
Abstract: A reconfigurable power-adaptive DT DeltaSigma ADC for intelligent 802.11n/WiMAX receivers (20 to 2.5MHz per I/Q) is presented. The intent is to replace complex analog baseband circuits with a combination of tunable one-pole filter, anti-alias filter and coarse VGA in Paramesh, J. et al (2006). Blocker filtering, fine variable-gain amplification and variable-BW channel selection are moved to the digital baseband. The SNR is optimized as a function of signal and out-of-band blocker power in Behbahani, F. et al, (2001) by reconfiguring the modulator order into one of 4 modes at constant fs, thereby keeping anti-aliasing unchanged. A 5b flash ADC integrated in the converter is the front end of a simple spectrum analyzer (SSA). Spectrum sensing and reconfigurability are accomplished without compromising ADC performance.
93 citations
"A 2.2dB NF, 4.9–6GHz direct convers..." refers background in this paper
...The receiver is designed to work with an over-sampled, high dynamic range sigma-delta ADC to relax analog filtering requirements, to lower cost and to improve yield [1]....
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TL;DR: In this paper, a low-power low flicker-noise receiver front-end for 915-MHz-band IEEE 802.15.4 standard in 0.18-/spl mu/m CMOS technology is implemented.
Abstract: A low-power low flicker-noise receiver front-end for 915-MHz-band IEEE 802.15.4 standard in 0.18-/spl mu/m CMOS technology is implemented. A power-constrained simultaneous noise and input matching low-noise amplifier (LNA) can be achieved by using a conventional inductive degeneration cascode amplifier with an extra gate-source capacitor. In combination with the LNA, a passive mixer showing low 1/f noise performance is adopted to convert the RF signal directly to the baseband signal. The measured results show a conversion gain of 30 dB and a noise figure of 3 dB with 1/f noise corner frequency of 30 kHz. Two-tone test measurements indicate -5-dBm input third-order intercept point and +45-dBm input second-order intercept point. The RF receiver front-end dissipates 2 mA from a 1.8-V supply.
70 citations
TL;DR: A current-mode interface between the downconversion mixer output and analog base band input together with a dynamic matching technique simultaneously improves the mixer linearity, allows the reduction of flicker noise due to the mixer switches, and minimizes the noise contribution of the analog baseband.
Abstract: In this paper, a 1.2-V RF front-end realized for the personal communications services (PCS) direct conversion receiver is presented. The RF front-end comprises a low-noise amplifier (LNA), quadrature mixers, and active RC low-pass filters with gain control. Quadrature local oscillator (LO) signals are generated on chip by a double-frequency voltage-controlled oscillator (VCO) and frequency divider. A current-mode interface between the downconversion mixer output and analog baseband input together with a dynamic matching technique simultaneously improves the mixer linearity, allows the reduction of flicker noise due to the mixer switches, and minimizes the noise contribution of the analog baseband. The dynamic matching technique is employed to suppress the flicker noise of the common-mode feedback (CMFB) circuit utilized at the mixer output, which otherwise would dominate the low-frequency noise of the mixer. Various low-voltage circuit techniques are employed to enhance both the mixer second- and third-order linearity, and to lower the flicker noise. The RF front-end is fabricated in a 0.13-/spl mu/m CMOS process utilizing only standard process options. The RF front-end achieves a voltage gain of 50 dB, noise figure of 3.9 dB when integrated from 100 Hz to 135 kHz, IIP3 of -9 dBm, and at least IIP2 of +30dBm without calibration. The 4-GHz VCO meets the PCS 1900 phase noise specifications and has a phase noise of -132dBc/Hz at 3-MHz offset.
38 citations
Additional excerpts
...The NF is the lowest in this frequency band for an integrated receiver with on-chip matching to the best of the author’s knowledge [4][5][ 6 ][7]....
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03 Jun 2007
TL;DR: In this paper, a 2-5.8 GHz receiver front-end dissipating 85 mW at 5 GHz while occupying 0.2 mm2 active area is fabricated as a demonstration of the combination of these concepts.
Abstract: This paper reviews architectures and circuit techniques suitable for highly integrated broadband receiver front-ends. Direct conversion simplifies the receiver architecture, resistive feedback LNAs reduce silicon area and current mode passive mixer operation improves the receiver linearity and reduces flicker noise. A 2-5.8 GHz receiver front-end dissipating 85 mW at 5 GHz while occupying 0.2 mm2 active area is fabricated as a demonstration of the combination of these concepts. It provides 44 dB of gain, 3.4 dB double side band noise figure, -21 dBm iIP3 and -15 dB of input matching.
11 citations
"A 2.2dB NF, 4.9–6GHz direct convers..." refers background in this paper
...The LO buffers are self-biased CMOS inverters [4], AC coupled to maintain 50% duty cycle....
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