A 2.2GHz subsampling PLL with 0.16ps rms jitter and −125dBc/Hz inband phase noise at 700µW loopcomponents power
16 Jun 2010pp 139140
Abstract: A dividerless PLL exploits a phase detector that directly samples the VCO with a reference clock. No VCO sampling buffer is used while dummy samplers keep the VCO spur <−56dBc. A modified inverter with low shortcircuit current acts as a power efficient reference clock buffer. The 2.2GHz PLL in 0.18µm CMOS achieves −125dBc/Hz inband phase noise with only 700µW loopcomponents power.
Topics: Phaselocked loop (58%), Voltagecontrolled oscillator (57%), Phase noise (57%), Jitter (56%), Phase detector (55%)
Summary (1 min read)
Introduction
 Clock multiplication PLLs with very low jitter have recently been proposed based on subsampling [1, 2] and injection locking [3, 4] .
 This paper describes a new SSPLL design aiming to drastically reduce the loopcomponents power while maintaining its superior inband phase noise performance.
 A concern of this bufferless direct VCO sampling is the disturbance to the VCO operation.
 For low noise sampling, the Ref sampling edge is highly critical and needs to be clean while the other Ref edge is not relevant.
 The proposed buffer thus greatly reduces power while maintaining the critical edge's noise performance.
Experimental results
 The PLL loopcomponents consume 0.7mW and the VCO 1.8mW.
 The worst case reference spur measured from 20 chips while changing Ref duty cycle is 56dBc. Fig. 5 summarizes the PLL performance and benchmarks it to low jitter PLLs.
 Note that the authors directly used a 55MHz sinewave XO as the PLL input while [3] used a 50MHz square wave and [4] used a 1GHz sine wave.
 Compared with [1] , the loopcomponents power is 8x lower while £ inband is only 1dB worse.
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A 2.2GHz SubSampling PLL with 0.16ps
rms
Jitter and
125dBc/Hz Inband Phase Noise at 700μW LoopComponents Power
Xiang Gao, Eric Klumperink, Gerard Socci*, Mounir Bohsali*, and Bram Nauta
University of Twente, Enschede, The Netherlands; *National Semiconductor, Santa Clara, California
+31534893811, X.Gao@utwente.nl, B.Nauta@utwente.nl
Abstract
A dividerless PLL exploits a phase detector that directly
samples the VCO with a reference clock. No VCO sampling
buffer is used while dummy samplers keep the VCO spur
<56dBc. A modified inverter with low shortcircuit current
acts as a power efficient reference clock buffer. The 2.2GHz
PLL in 0.18μm CMOS achieves 125dBc/Hz inband phase
noise with only 700μW loopcomponents power.
Introduction
Clock multiplication PLLs with very low jitter have recently
been proposed based on subsampling [1,2] and injection
locking [3,4]. In a PLL, the VCO dominates the outofband
phase noise while the loopcomponents dominate the inband
phase noise. The subsampling (SS) PLL [1,2] can achieve
very low inband phase noise because: 1) divider noise is
eliminated; 2) the phase detector (PD) and charge pump (CP)
noise is not multiplied by N
2
. This paper describes a new
SSPLL design aiming to drastically reduce the
loopcomponents power while maintaining its superior
inband phase noise performance.
Proposed Low Power SSPLL
Fig. 1(a) shows the low power SSPLL architecture. A
subsampling phase detector (SSPD) samples the VCO with a
reference clock Ref and converts VCO phase error into
sampled voltage variation. A CP converts the sampled voltage
to current. A Pulser controls the CP gain and simplifies the
SSPD design to a trackandhold [1]. A frequency locked loop
ensures correct frequency locking and is disabled after locking
to save power. In a SSPLL the PD and CP noise contributions
are low and thus their power can be scaled down progressively.
The VCO and Ref buffers for the SSPD then become the
bottlenecks for low power. In [1], they account for 30% and
60% of the total loopcomponents power, respectively. In this
design, we propose two techniques to alleviate these
bottlenecks: 1) direct sampling of the VCO without buffer
while keeping the disturbance to the VCO low; 2) power
efficient Ref buffering with drastically reduced shortcircuit
current.
Fig. 2 shows the LC VCO and SSPD schematic. Different
from [1], no buffer is used between the VCO and SSPD
samplers. This saves power as buffers running at f
VCO
are
power consuming. The samplers use PMOS switches since the
VCO DC level is high. A concern of this bufferless direct
VCO sampling is the disturbance to the VCO operation. When
Ref turns on/off the sampling switch, the VCO is
loaded/unloaded by the sampling capacitors C
sam
. The VCO
load and thus f
VCO
is changed resulting in binary frequency
shift keying (BFSK), causing spurs at integer multiples of f
ref
.
In order to reduce this effect, dummy samplers are added as
(a)
Frequency locked loop
PFD/CP
with dead zone
÷ N
VCOVCO
X
O
VCO
Low Power
Buffer
CP
Pulser
Ref
N
∑∑

+
F
LF
(s)
K
VCO
/s
++ ++ ++
++
nref ,
φ
[Ф
out
]
nCP
i
, nLF
v
, nVCO,
φ
[Ф
ref
]
K
CP
++
nsam
v
,
K
SSPD
(b)
SSPD
v
sam
For differential sampling, K
SSPD
=2A
VCO
Fig. 1. SubSampling PLL (a) architecture, (b) phase domain model.
C
sam
=10fF
Ref
Ref
V
tune
VCO+
VCO
dummy sampler
C
sam
V
sam+
dummy sampler
10fF
10fF
sampler
sampler
3b Cap Array
C
sam
=10fF
9nH
V
sam
dummy CP
Fig. 2. Schematic of the VCO and SSPD.
shown in Fig. 2, which are controlled by the inverted Ref. A
transmission gate (not shown in the figure) compensates the
inverter delay. Due to the complementary switching of the
sampler and its dummy, the VCO load does not change over
time and the BFSK effect is compensated. In reality, the
compensation is not perfect due to capacitor mismatch ΔC
sam
between the sampler and its dummy. Since ΔC
sam
scales with
the value of C
sam
, it is desirable to have a small C
sam
for a low
spur level. However, a smaller C
sam
means more sampler noise.
With the phase domain model in Fig. 1(b), the inband phase
noise due to the samplers can be derived as
).log(
,
refVCOsam
SSPDbandin
fAC
kT
⋅⋅
=
−
2
2
10L
With f
ref
=55MHz and VCO amplitude A
VCO
=0.4V, C
sam
is
chosen to be 10fF resulting in 136dBc/Hz, 10% of the
targeted 126dBc/Hz of [1].
In order to properly sample the GHz VCO, Ref should have a
steep sampling edge with a slew rate (SR) higher than the VCO
SR. In most applications, Ref is derived from a sine wave
crystal oscillator (XO) which often has a much lower SR than
the VCO since f
ref
<< f
VCO
. A buffer converting the sine XO
into a square wave Ref is thus needed. In the 10sofMHz
frequency range, a CMOS inverter buffer is more power
efficient than a CML buffer as it mainly consumes dynamic
power. Noise on Ref is critical for inband phase noise as it is
still multiplied by N
2
when transferred to the SSPLL output;
see Fig. 1(b). Thus large inverters need to be used at the
expense of power. As the input SR is low and output SR high,
power is wasted due to the “shortcircuit” current caused by
simultaneous conduction of the NMOS and PMOS transistors
during switching.
In a sampling process, only one of the two clock edges is
used as the sampling edge. In this SSPD design (Fig. 2), the
Ref rising edge is the sampling edge. For low noise sampling,
the Ref sampling edge is highly critical and needs to be clean
while the other Ref edge is not relevant. Fig. 3 shows the
proposed Ref buffer, which exploits this property to drastically
reduce power. A similar circuit has been used in [2] to control
the Ref duty cycle. Here we exploit it to achieve low power.
The idea is to directly convey the critical edge and reposition
the other noncritical edge at a convenient place to avoid the
shortcircuit current. The buffer core is an inverter with an
NMOS N1 and a PMOS P1. N1 is directly connected to XO as
in a conventional inverter, while a timing control circuit (TCC)
is inserted between P1 and XO. The TCC consists of two delay
cells Δt
1
and Δt
2
and a few standard logic gates. It generates a
narrow pulse V
GP
from the XO and controls the gate of P1. As
shown in Fig. 3, Δt
1
and Δt
2
are set such that the time when V
GP
is low (P1 conducts) and the time when XO is higher than the
threshold of N1 (N1 conducts) are nonoverlapping. Since f
ref
is low, this timing plan is easy to achieve. In this way, N1 and
P1 will not conduct simultaneously thereby eliminating the
shortcircuit current. Since the Ref rising edge is the critical
sampling edge, the size of N1 is kept big to maintain a low
sampling edge noise, while the TCC and P1 use small sizes to
save power as they only add noise to the noncritical edge. The
first block Inv1 in the TCC is a conventional inverter and has
the slow XO as its input. It thus still has shortcircuit current,
but the contribution to the total buffer power is negligible as its
size is small. The proposed buffer thus greatly reduces power
while maintaining the critical edge’s noise performance.
Experimental results
The 2.2GHz PLL was fabricated in standard 1.8V 0.18µm
CMOS with an active area of 0.4 x 0.5 mm
2
(Fig. 4). Measured
inpackage with a 1.8V
pp
55MHz XO as input, the inband
phase noise
£
inband
at 200kHz is 125dBc/Hz as shown in Fig.
4. The jitter integrated from 10kHz to 100MHz is 0.16ps
rms
.
The PLL loopcomponents consume 0.7mW and the VCO
1.8mW. The worst case reference spur measured from 20 chips
while changing Ref duty cycle is 56dBc. Fig. 5 summarizes
the PLL performance and benchmarks it to low jitter PLLs.
This design has the best PLL FOM. Note that we directly used
a 55MHz sinewave XO as the PLL input while [3] used a
50MHz square wave and [4] used a 1GHz sine wave.
Compared with [1], the loopcomponents power is 8x lower
while
£
inband
is only 1dB worse. Compared with [2], the
loopcomponents power is 3x lower while
£
inband
is 4dB better.
References
[1] X. Gao, et al., “A 2.2GHz 7.6mW subsampling PLL with
126dBc/Hz inband phase noise and 0.15ps
rms
jitter in 0.18μm
CMOS,” ISSCC, pp. 392  393, Feb. 2009.
[2] X. Gao, et al., “SpurReduction Techniques for PLLs Using
SubSampling Phase Detection,” ISSCC, pp. 474475, Feb. 2010.
[3] B. Helal, et al., “A low jitter programmable clock multiplier based
on a pulse injectionlocked oscillator with a highlydigital tuning
loop,” J. SolidState Circuits, pp.1391–1400, May 2009.
[4] J. Lee and H. Wang, “Study of subharmonically injectionlocked
PLLs,” J. SolidState Circuits, pp.1539–1553, May 2009.
XO
V
GP
&
Inv1 toggle
V
th
of N1
V
GP
810/0.3
20/0.18
Δt
1
Δt
2
)
.
/
.
./.
(
18001
18041
N1 on
Δt
1
Timing Control Circuit (TCC)
N1
P1
Inv1
P1 on
Δt
2
Inv
out
XO
Inv
out
Ref
Fig. 3. Schematic and timing diagram of the low power buffer.
VCO
Loop
Filter
0.4
mm
0.5 mm
PD
CP
Fig. 4. Measured PLL output phase noise.
This Work
[1] [2] [3] [4chip A] [4chip B]
f
out
(GHz) 2.21 2.21 2.21
3.2 20 20
f
ref
(MHz)
55.25 55.25 55.25 50 1000 2500
RMS jitter
σ
t
(ps)
0.16
(10k100M)
0.15
(10k40M)
0.3
(10k100M)
0.13
(10040M)
0.11
(50k80M)
0.048
(50k80M)
Inband phase
noise (dBc/Hz)
125
@200kHz
126
@200kHz
121
@200kHz
127
@1MHz
113
@1MHz
123
@1MHz
Ref Spur (dBc)
(# of sample)
56
(#=20)
46
(#=1)
80
(#=20)
64
(#=1)
46
(#=1)
55
(#=1)
PLL Power P (mW)
2.5
7.6
3.8
28.6 38 105
LoopComponents
Power (mW)
0.7
5.8 2   
PLL FOM (dB)
252 248 244 243
243 246
Active area (mm
2
) 0.20 0.18 0.20 0.40
<0.45 <0.32
Technology (CMOS)
0.18μm 0.18μm 0.18μm 0.13μm 90nm 90nm
This Work
[1] [2] [3] [4chip A] [4chip B]
f
out
(GHz) 2.21 2.21 2.21
3.2 20 20
f
ref
(MHz)
55.25 55.25 55.25 50 1000 2500
RMS jitter
σ
t
(ps)
0.16
(10k100M)
0.15
(10k40M)
0.3
(10k100M)
0.13
(10040M)
0.11
(50k80M)
0.048
(50k80M)
Inband phase
noise (dBc/Hz)
125
@200kHz
126
@200kHz
121
@200kHz
127
@1MHz
113
@1MHz
123
@1MHz
Ref Spur (dBc)
(# of sample)
56
(#=20)
46
(#=1)
80
(#=20)
64
(#=1)
46
(#=1)
55
(#=1)
PLL Power P (mW)
2.5
7.6
3.8
28.6 38 105
LoopComponents
Power (mW)
0.7
5.8 2   
PLL FOM (dB)
252 248 244 243
243 246
Active area (mm
2
) 0.20 0.18 0.20 0.40
<0.45 <0.32
Technology (CMOS)
0.18μm 0.18μm 0.18μm 0.13μm 90nm 90nm
PLL Power (mW)
10
0
10
1
10
2
10
3
10
0
Jitter Variance (ps
2
)
10
1
10
2
10
3
07_17.1
06_32.5
00_12.5
FOM
=

2
6
0
d
B
F
O
M
=

2
3
0
d
B
F
O
M
=

2
4
0
d
B
08_19.1
04_5.5
03_10.3
F
O
M
=

2
5
0
d
B
This work
[1]
[3]
[4A]
[4B]
]
1
)
1
log[(10
2
m
W
P
s
FOM
t
⋅=
σ
[2]
Fig. 5. Performance summary and comparison. The unreferenced
ones are the PLL designs with the best FOM in last 10 years’ ISSCC,
marked with “Year_PaperNumber”.
Citations
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07 Apr 2011
TL;DR: This paper introduces a fractionalN PLL based on a 1b TDC, achieving jitter of 560fsrms (from 3kHz to 30MHz) at 4.5mW power consumption, even in the worstcase of fractional spur falling within the PLL bandwidth.
Abstract: This paper introduces a ΔΣ fractionalN digital PLL based on a singlebit TDC. A digitaltotime converter, placed in the feedback path, cancels out the quantization noise introduced by the dithering of the frequency divider modulus and permits to achieve low noise at low power. The PLL is implemented in a standard 65nm CMOS process. It achieves  102dBc/Hz phase noise at 50kHz offset and a total absolute jitter below 560 fsrms (integrated from 3 kHz to 30 MHz), even in the worstcase of a 42dBc inband fractional spur. The synthesizer tuning range spans from 2.92 GHz to 4.05 GHz with 70Hz resolution. The total power consumption is 4.5 mW, which leads to the best jitterpower tradeoff obtained with a fractionalN synthesizer. The synthesizer demonstrates the capability of frequency modulation up to 1.25Mb/s data rate.
182 citations
••
Abstract: This paper presents phaselocked loop (PLL) referencespur reduction design techniques exploiting a subsampling phase detector (SSPD) (which is also referred to as a sampling phase detector). The VCO is sampled by the reference clock without using a frequency divider and an amplitude controlled charge pump is used which is inherently insensitive to mismatch. The main remaining source of the VCO reference spur is the periodic disturbance of the VCO by the sampling at the reference frequency. The underlying VCO sampling spur mechanisms are analyzed and their effect is minimized by using dummy samplers and isolation buffers. A dutycyclecontrolled reference buffer and delaylocked loop (DLL) tuning are proposed to further reduce the worst case spur level. To demonstrate the effectiveness of the proposed spur reduction techniques, a 2.21 GHz PLL is designed and fabricated in 0.18 μm CMOS technology. While using a high loopbandwidthtoreferencefrequency ratio of 1/20, the reference spur measured from 20 chips is <; 80 dBc. The PLL consumes 3.8 mW while the inband phase noise is 121 dBc/Hz at 200 kHz and the output jitter integrated from 10 kHz to 100 MHz is 0.3psrms.
93 citations
••
TL;DR: This paper proposes constantslope charging as a method to realize a DTC with intrinsically better integral nonlinearity (INL) compared to the popular variableSlope method.
Abstract: A digitaltotime converter (DTC) controls time delay by a digital code, which is useful, for example, in a sampling oscilloscope, fractionalN PLL, or timeinterleaved ADC. This paper proposes constantslope charging as a method to realize a DTC with intrinsically better integral nonlinearity (INL) compared to the popular variableslope method. The proposed DTC chip realized in 65 nm CMOS consists of a voltagecontrolled variabledelay element (DTCcore) driven by a 10 bit digitaltoanalog converter. Measurements with a 55 MHz crystal clock demonstrate a fullscale delay programmable from 19 ps to 189 ps with a resolution from 19 fs to 185 fs. As available oscilloscopes are not good enough to reliably measure such high timing resolution, a frequencydomain method has been developed that modulates a DTC edge and derives INL from spur strength. An INL of 0.17% at 189 ps fullscale delay and 0.34% at 19 ps are measured, representing 8–9 bit effective INLlimited resolution. Output rms jitter is better than 210 fs limited by the test setup, while the DTC consumes 1.8 mW.
68 citations
••
28 Mar 2013
TL;DR: A dividerless SIPLL with selfadjusted injection timing is presented, which achieves not only low phase noise, but also low power in a lowphasenoise subharmonically injectionlocked PLL.
Abstract: A lowphasenoise phaselocked loop (PLL) is widely used in clock generation, frequency synthesis, and data conversion. In a PLL using a subsampling phase detector (SSPD) achieves not only low phase noise, but also low power. In a lowphasenoise subharmonically injectionlocked PLL (SIPLL) is presented. The injection timing of a SIPLL is sensitive to the process, voltage, and temperature (PVT) variations. In addition, the divider of a SIPLL [35] cannot be powered down to save the power as in [1, 2]. In this paper, a dividerless SIPLL with selfadjusted injection timing is presented.
53 citations
••
TL;DR: In this paper, a lownoise cascaded PLL is proposed where an integerN digital bangbang P LL is used to multiply a 50 MHz reference to an 800 MHz clock that is fed to a ΔΣ fractionalN PLL to generate 2.55to3 GHz output.
Abstract: In this paper, a lownoise cascaded PLL is proposed where an integerN digital bangbang PLL is used to multiply a 50 MHz reference to an 800 MHz clock that is fed to a ΔΣ fractionalN PLL to generate 2.55to3 GHz output. In order to minimize the jitter of the 800 MHz clock, a reference injection scheme using dualpulse ring oscillator is employed. Quantization noise from the deltasigma modulator is suppressed without any noise cancellation techniques owing to the high operating frequency of the fractionalN PLL. Prototype implemented in 0.13 μm CMOS process achieves the worstcase RMS jitter of 356 fsrms over 100 Hz to 40 MHz integration bandwidth, while consuming 14.2 mW from a 1.2 V supply. The worstcase fractional spur measured over 7 different chips is 53.9 dBc and the reference spur is 84 dBc.
45 citations
References
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••
TL;DR: A complete analysis on subharmonically injectionlocked PLLs develops fundamental theory for subharmonic locking phenomenon, which explains the noise shaping phenomenon, locking range and behavior, PVT tolerance, and pseudo locking issue.
Abstract: A complete analysis on subharmonically injectionlocked PLLs develops fundamental theory for subharmonic locking phenomenon. It explains the noise shaping phenomenon, locking range and behavior, PVT tolerance, and pseudo locking issue. All of the analyses are verified by real chip measurements. Two 20GHz PLLs based on the proposed theory are designed and fabricated in 90nm CMOS technology to demonstrate the superiority and robustness of this technique. The first chip aims at lownoise/lowpower/highdivideratio design, achieving 149fs rms jitter (integrated from 100 Hz to 1 GHz) while consuming 38 mW from a 1.3V supply. The second prototype shoots for the lowest noise performance, presenting 85fs rms jitter (the same integration interval) with a power dissipation of 105 mW. The jitter generation (from 50 kHz to 80 MHz) measures 48 fs, which is at least twice as small as that of any other known circuits.
163 citations
••
TL;DR: A pulse injectionlocked oscillator (PILO) that provides low jitter clock multiplication of a clean input reference clock using a mostlydigital feedback circuit that provides continuous tuning of the oscillator such that its natural frequency is locked to the injected frequency.
Abstract: This paper introduces a pulse injectionlocked oscillator (PILO) that provides low jitter clock multiplication of a clean input reference clock. A mostlydigital feedback circuit provides continuous tuning of the oscillator such that its natural frequency is locked to the injected frequency. The proposed system is demonstrated with a prototype consisting of a custom 0.13 mum integrated circuit with active area of 0.4 mm2 and core power of 28.6 mW, along with an FPGA, a discrete DAC and a simple RC filter. Using a low jitter 50 MHz reference input, the PILO prototype generates a 3.2 GHz output with integrated phase noise, reference spur, and estimated deterministic jitter of 130 fs (rms), 63.9 dBc, and 200 fs (peaktopeak), respectively.
92 citations
••
29 May 2009TL;DR: This paper presents a 2.2GHz clockgeneration PLL that uses a phasedetector/chargepump (PD/CP) that subsamples the VCO output with the reference clock and achieves a low inband phase noise values at low power.
Abstract: A clock with low phasenoise/jitter is a prerequisite for highperformance ADCs, wireline and optical data links and radio transceivers. This paper presents a 2.2GHz clockgeneration PLL. It uses a phasedetector/chargepump (PD/CP) that subsamples the VCO output with the reference clock. The PLL does not need frequency divider in locked state and achieves a low inband phase noise values at low power.
63 citations
••
18 Mar 2010TL;DR: This paper proposes design techniques based on subsampling phase detection to reduce the reference spur of a 2.2GHz PLL to −80dBc at a high loopbandwidthtoreferencefrequency ratio (fBW/fref) of 1/20.
Abstract: In PLL designs, a wide loop bandwidth is often desired as it offers fast settling time, reduces onchip loop filter area and sensitivity of the VCO to pulling. The reference spur is a major issue when the bandwidth is increased, because ripples on the VCO control line undergo less filtering by the loop filter. This paper proposes design techniques based on subsampling phase detection to reduce the reference spur of a 2.2GHz PLL to −80dBc at a high loopbandwidthtoreferencefrequency ratio (f BW /f ref ) of 1/20.
22 citations
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