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Fig. 5. Performance summary and comparison. The un-referenced ones are the PLL designs with the best FOM in last 10 years’ ISSCC, marked with “Year_PaperNumber”.
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Proceedings Article
•
DOI
•
A 2.2GHz sub-sampling PLL with 0.16ps rms jitter and −125dBc/Hz in-band phase noise at 700µW loop-components power
[...]
Xiang Gao
1
,
Eric A.M. Klumperink
1
,
Gerard G. Socci
2
,
Mounir Bohsali
2
,
Bram Nauta
1
- Show less
+1 more
•
Institutions (2)
University of Twente
1
,
National Semiconductor
2
16 Jun 2010
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