A 2.5-dB Insertion Loss, DC-60 GHz CMOS SPDT Switch in 45-nm SOI
01 Nov 2011-pp 1-4
TL;DR: In this article, a single-pole double-throw (SPDT) switch operating from DC to 60 GHz is presented, which exhibits a measured insertion loss of less than 1.7 dB at 45 GHz and less than 2.5 dB at 60 GHz.
Abstract: This paper presents a single-pole double-throw (SPDT), transmit/receive (T/R) switch operating from DC to 60 GHz. The SPDT switch is based on a series-shunt circuit with broadband input and output matching circuits and is implemented in a partially-depleted, 45-nm silicon-on-insulator (SOI) process. A buried oxide (BOX) layer is demonstrated to minimize substrate coupling. The switch exhibits a measured insertion loss of less than 1.7 dB at 45 GHz and less than 2.5 dB at 60 GHz with an isolation of greater than 25 dB at 45 GHz. To our knowledge, this is the lowest insertion loss demonstrated for an SPDT switch at 60 GHz in a CMOS process. With a control voltage of 1.2 V, the measured P1dB and IIP3 are 7.1 dBm and 18.2 dBm, respectively. The active chip area is 0.18×0.22 mm2.
Citations
More filters
TL;DR: In this article, the analysis and design of saturated silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) switches for millimeter-wave applications is described.
Abstract: This paper describes the analysis and design of saturated silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) switches for millimeter-wave applications. A switch optimization procedure is developed based on detailed theoretical analysis and is then used to design multiple switch variants. The switches utilize IBM's 90-nm 9HP technology, which features SiGe HBTs with peak f T/ fmax of 300/350 GHz. Using a reverse-saturated configuration, a single-pole double-throw switch with a measured insertion loss of 1.05 dB and isolation of 22 dB is achieved at 94 GHz after de-embedding pad losses. The switch draws 5.2 mA from a 1.1-V supply, limiting power consumption to less than 6 mW. The switching speed is analyzed and the simulated turn-on and turn-off times are found to be less than 200 ps. A technique is also introduced to significantly increase the power-handling capabilities of saturated SiGe switches up to an input-referred 1-dB compression point of 22 dBm. Finally, the impact of RF stress on this novel configuration is investigated and initial measurements over a 48-h period show little performance degradation. These results demonstrate that SiGe-based switches may provide significant benefits to millimeter-wave systems.
81 citations
Cites background from "A 2.5-dB Insertion Loss, DC-60 GHz ..."
...In the on-state, when , the equivalent on-state resistance is dominated by the channel resistance, shown in (3) as follows: (3) Since the off-state capacitance is normally resonated out with an inductive shunt stub, it is the equivalent off-state resistance which limits the performance of the…...
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18 Dec 2014
Abstract: Improvements to the GeTe inline phase-change switch (IPCS) technology have resulted in a record-performing radio-frequency (RF) switch. An ON-state resistance of 0.9 Ω (0.027 Ω·mm) with an OFF-state capacitance and resistance of 14.1 fF and 30 kΩ, respectively, were measured, resulting in a calculated switch cutoff frequency (Fco) of 12.5 THz. This represents the highest reported Fco achieved with chalcogenide switches to date. The threshold voltage (Vth) for these devices was measured at 3V and the measured third-order intercept point (TOI) was 72 dBm. Single-pole, single-throw (SPST) switches were fabricated, with a measured insertion loss less than 0.15 dB in the ON-state, and 15dB isolation in the OFF-state at 18 GHz. Single-pole, double-throw (SPDT) switches were fabricated using a complete backside process with through-substrate vias, with a measured insertion loss 0.25 dB, and 35dB isolation.
51 citations
04 Jun 2017
TL;DR: In this article, a 0 mW two-channel 28 GHz bi-directional phased array chip was presented using flip-chip interconnects in 45nm CMOS SOI.
Abstract: This paper presents a 0 mW two-channel 28 GHz bi-directional phased-array chip packaged using flip-chip interconnects in 45nm CMOS SOI. The design alternates switched-LC phase shifters with switched attenuators to result in 5-bit phase control with an rms gain and phase error 1dB of 5 dBm. In the TX mode, the measured output P 1dB is −2 dBm. This work presents an efficient solution for the construction of high-linearity and high-power phased-array base-stations by combining GaAs front-ends with a passive silicon core chip.
39 citations
01 Dec 2014
TL;DR: The Super-Lattice Castellated Field Effect Transistor (SLCFET) as mentioned in this paper is a GaN super-lattice channel with a 3D gate.
Abstract: NGES reports the development of a novel transistor structure based on a GaN super-lattice channel with a 3D gate, named the SLCFET (Super-Lattice Castellated Field Effect Transistor). Transistor measurements provided median values of I MAX >2.7 A/mm, V PINCH = −8V, with R ON =0.41 Ω-mm and C OFF =0.19 pF/mm, for an RF switch FOM of F CO =2.1 THz.
38 citations
Additional excerpts
...This has been true for FET based RF switches in a variety of different technologies, including CMOS [7], Silicon on Sapphire [8], GaAs pHEMTs [9], or InP [10], ABCS [11] and GaN HEMTs [12]....
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...Values for the RF switch figure of merit in FETs ranges from ~360 GHz for Si CMOS on SOI [14], to ~500 GHz in GaAs pHEMTs [15] and GaN HEMTs [12], to ~840 GHz for InP HEMTs [10]....
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TL;DR: In this paper, the authors present passive integrated circuits for millimeter-wave transmitters and receivers implemented in a 45-nm CMOS silicon-on-insulator (SOI) process.
Abstract: This paper presents passive integrated circuits for millimeter-wave transmitters and receivers implemented in a 45-nm CMOS silicon-on-insulator (SOI) process. The advantages of SOI over bulk CMOS are discussed for millimeter-wave passive circuits. First, a single pole double throw (SPDT) switch demonstrates a measured insertion loss of less than 1.7 dB at 45 GHz and third-order intermodulation intercept point (IIP3) of 18.2 dBm. Second, a double-balanced passive in-phase/quadrature (I/Q) mixer exhibits a conversion loss of 8.35 dB at 44 GHz and IIP3 of 15.5 dBm. At a fixed IF of 200 MHz, the minimum I/Q gain and phase imbalance is 0.25 dB and 1.9°. The passive mixer and SPDT switch results demonstrate a record minimum insertion loss and linearity performance for the passive millimeter-wave circuits.
36 citations
Cites background from "A 2.5-dB Insertion Loss, DC-60 GHz ..."
...9, the SPDT results in an insertion loss of 1.7 dB at 45 GHz and less than 2.5 dB at 60 GHz with excellent input and output match....
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...However, increasing the FET width increases parasitic capacitance and contributes to worse linearity, port-to-port isolation, and the requirement for higher local oscillator (LO) power....
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References
More filters
TL;DR: In this article, a single-pole double-throw transmit/receive switch for 30-V applications has been fabricated in a 05/spl mu/m CMOS process, which exhibits a 07-dB insertion loss, a 17-dBm power 1-dB compression point (P/sub 1 dB/), and a 42-dB isolation at 928 MHz.
Abstract: A single-pole double-throw transmit/receive switch for 30-V applications has been fabricated in a 05-/spl mu/m CMOS process An analysis shows that substrate resistances and source/drain-to-body capacitances must be lowered to decrease insertion loss The switch exhibits a 07-dB insertion loss, a 17-dBm power 1-dB compression point (P/sub 1 dB/), and a 42-dB isolation at 928 MHz The low insertion loss is achieved by optimizing the transistor widths and bias voltages, by minimizing the substrate resistances, and by dc biasing the transmit and receive nodes, which decreases the capacitances while increasing the power 1-dB compression point The switch has adequate insertion loss, isolation, P/sub 1 dB/, and IP/sub 3/ for a number of 900-MHz ISM band applications requiring a moderate peak transmitter power level (/spl sim/15 dBm)
176 citations
Book•
IBM1
TL;DR: In this article, the authors introduce the student or practicing engineer to SOI device physics and its fundamental idiosyncrasies, and walk the reader through realizations of these mechanisms which are observed in common high-speed microprocessor designs.
Abstract: Market demand for microprocessor performance has motivated continued scaling of CMOS through a succession of lithography generations. Quantum mechanical limitations to continued scaling are becoming readily apparent. Partially Depleted Silicon-on-Insulator (PD-SOI) technology is emerging as a promising means of addressing these limitations. It also introduces additional design complexity which must be well understood. SOI Circuit Design Concepts first introduces the student or practicing engineer to SOI device physics and its fundamental idiosyncrasies. It then walks the reader through realizations of these mechanisms which are observed in common high-speed microprocessor designs. Rules of thumb and comparisons to conventional bulk CMOS are offered to guide implementation. SOI's ultimate advantage, however, may lie in the unique circuit topologies it supports; a number of these novel new approaches are described as well. SOI Circuit Design Concepts draws upon the latest industry literature as well as the firsthand experiences of its authors. It is an ideal introduction to the concepts of governing SOI use and provides a firm foundation for further study of this exciting new technology paradigm.
151 citations
"A 2.5-dB Insertion Loss, DC-60 GHz ..." refers background in this paper
...Section IV presents the measurements and a comparison of this work to other SPDT switches....
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TL;DR: In this paper, a fully integrated ultra-broadband transmit/receive (T/R) switch was developed using nMOS transistors with a deep n-well in a standard 0.18mum CMOS process, and demonstrates unprecedented insertion loss, isolation, power handling, and linearity.
Abstract: A fully integrated ultra-broadband transmit/receive (T/R) switch has been developed using nMOS transistors with a deep n-well in a standard 0.18-mum CMOS process, and demonstrates unprecedented insertion loss, isolation, power handling, and linearity. The new CMOS T/R switch exploits patterned-ground-shield on-chip inductors together with MOSFET's parasitic capacitances to synthesize artificial transmission lines, which result in low insertion loss over an extremely wide bandwidth. Negative bias to the bulk or positive bias to the drain of the MOSFET devices with floating bulk is used to reduce effects of the parasitic diodes, leading to enhanced linearity and power handling for the switch. Within dc-10, 10-18, and 18-20 GHz, the developed CMOS T/R switch exhibits insertion loss of less than 0.7, 1.0, and 2.5 dB and isolation between 32-60, 25-32, and 25-27 dB, respectively. The measured 1-dB power compression point and input third-order intercept point reach as high as 26.2 and 41 dBm, respectively. The new CMOS T/R switch has a die area of only 230 mumtimes250 mum. The achieved ultra-broadband performance and high power-handling capability, approaching those achieved in GaAs-based T/R switches, along with the full-integration ability confirm the usefulness of switches in CMOS technology, and demonstrate their great potential for many broadband CMOS radar and communication applications
130 citations
TL;DR: In this paper, the authors present designs and measurements of Ka-band single-pole single-throw (SPST) and singlepole double throw (SPDT) 0.13-CMOS switches.
Abstract: This paper presents designs and measurements of Ka-band single-pole single-throw (SPST) and single-pole double-throw (SPDT) 0.13-CMOS switches. Designs based on series and shunt switches on low and high substrate resistance networks are presented. It is found that the shunt switch and the series switch with a high substrate resistance network have a lower insertion loss than a standard designs. The shunt SPST switch shows an insertion loss of 1.0 dB and an isolation of 26 dB at >35 GHz. The series SPDT switch with a high substrate resistance network shows excellent performance with 2.2-dB insertion loss and isolation at 35 GHz, and this is achieved using two parallel resonant networks. The series-shunt SPDT switch using deep n-well nMOS transistors for a high substrate resistance network results in an insertion loss and isolation of 2.6 and 27 dB, respectively, at 35 GHz. For series switches, the input 1-dB compression point (1P1) can be significantly increased to with the use of a high substrate resistance design. In contrast, of shunt switches is limited by the self-biasing effect to 12 dBm independent of the substrate resistance network. The paper shows that, with good design, several 0.13- CMOS designs can be used for state-of-the-art switches at 26-40 GHz.
95 citations
"A 2.5-dB Insertion Loss, DC-60 GHz ..." refers background or methods in this paper
...The power handling is limited by the voltage swing at the gate of the shunt transistor due to the self-biasing effect [ 1 ]....
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...Previously, mm-wave SPDT switches have been demonstrated using a range of bulk CMOS processes from 180nm to advanced 45-nm lithography nodes [ 1 ]‐[7]....
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NEC1
TL;DR: In this article, a novel ohmic electrode sharing technology (OEST) has been developed for MMIC switches with series-shunt FET configuration for millimeter-wave communications and radar systems.
Abstract: Compact DC-60-GHz heterojunction field-effect transistor (HJFET) monolithic-microwave integrated-circuit (MMIC) switches have been demonstrated for millimeter-wave communications and radar systems To reduce the MMIC chip size, a novel ohmic electrode-sharing technology (OEST) has been developed for MMIC switches with series-shunt FET configuration Four FET's of the series-shunt single-pole double-throw (SPDT) MMIC switch were integrated into an area of approximately 0018 mm/sup 2/ The developed MMIC switches have a high power-handling capability with low insertion loss (IL) and high isolation (Iso) at millimeter-wave frequencies From DC to 60 GHz, the single-pole single-throw (SPST) MMIC switch achieved the IL and Iso of better than 164 and 206 dB, respectively At 40 GHz, the IL increases by 1 dB at the input power of 21 dBm A novel large-signal FET model for the switch circuit is presented The simulated power-transfer performance shows the excellent agreement with the measured one The developed MMIC switches will contribute to the low-cost and high-performance millimeter-wave communications and radar systems
63 citations