A 200PS differential CMOS delay element for 10 GHz ultra wideband wireless receivers
01 Dec 2012-pp 713-716
TL;DR: Design of a novel selective band delay element and its performance gain over nominal low pass LC ladder based delay element is demonstrated and maximum dynamic power consumption is found to be 6μW.
Abstract: Design of a novel selective band delay element and its performance gain over nominal low pass LC ladder based delay element is demonstrated. The delay element uses three 2nd order all pass filter as its core element and achieves a delay of 200 ± 10 ps within 6.8 GHz to 12.9 GHz range. The circuit is implemented using 130 nm RF CMOS technology. Total area of the circuit is 0.88mm × 0.86mm without bondpad and 0.88mm × 1.06mm with bondpad. The circuit uses only passive elements, thus there is no static power consumption. Maximum dynamic power consumption is found to be 6μW.
Citations
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01 Jan 2003
TL;DR: In this paper, an expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems.
Abstract: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0
207 citations
Dissertation•
01 Oct 2011
7 citations
TL;DR: Experimental results show that DTDUs, with negligible power overhead, have higher immunity to supply voltage and process variations while taking less silicon area and enhancing heat dissipation, compared to traditional delay units.
Abstract: Delay units play an important role in bitline design for on-chip memory. Traditional delay units can be categorized into two types: passive ones and active ones. In this paper, a novel hybrid delay unit (combination of passive and active ones) using dummy through-silicon vias (TSVs) in 3-D on-chip memory is proposed for modern microprocessors. Dummy TSV delay units (DTDUs) are developed in multilevel bitlines of a 128-kB 3-D on-chip memory with 180- and 45-nm CMOS technologies. Experimental results show that DTDUs, with negligible power overhead, have higher immunity to supply voltage and process variations while taking less silicon area and enhancing heat dissipation, compared to traditional delay units.
1 citations
Cites background from "A 200PS differential CMOS delay ele..."
...variation of active delay units increases rapidly as feature size become smaller [14], the hybrid delay unit—DTDUs will have much more stable delay time [58]....
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...[58] propose another delay cell of inductors and capacitors which can keep the delay variation as low as 5%....
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01 Dec 2016
TL;DR: An integrated solution for phase demodulation in such an architecture that achieves 2 GBaud/s with 8th order differential phase shift keying at a frequency of 60 GHz and is realized in a 130nm SiGe BiCMOS technology.
Abstract: With increasing data rates in communication systems, the call for wideband transceiver solutions capable of processing complex modulation schemes is getting stronger. Unfortunately, this goes along with power hungry systems and more complex integrated circuits. A novel receiver architecture, which addresses these issues, is based on the simultaneous phase and amplitude regenerative sampling system. Its system exploits switched injection-locked oscillators and their capability to regenerate signals with a gain of over 40 dB. This paper demonstrates an integrated solution for phase demodulation in such an architecture. The proposed concept uses the low complex but efficient self-mixing principle and consists mainly of double-balanced Gilbert mixers, amplifiers, a delay line and passive power dividers. The detection of the phase is achieved through self-mixing the regenerated signal with one path delayed by a symbol period. The architecture achieves 2 GBaud/s with 8th order differential phase shift keying at a frequency of 60 GHz and is realized in a 130nm SiGe BiCMOS technology.
1 citations
Cites methods from "A 200PS differential CMOS delay ele..."
...Delay Element The delay element used in the system is based on a differential second order allpass filter as described in [6]....
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References
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Journal Article•
TL;DR: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems.
Abstract: 53 ■ IEEE CIRCUITS & DEVICES MAGAZINE ■ NOVEMBER/DECEMBER 2005 THE DESIGN OF CMOS RADIOFREQUENCY INTEGRATED CIRCUITS, 2ND ED By Thomas Lee, Cambridge University Press, 2003. All-CMOS radio transceivers and system-on-a-chip are rapidly making inroads into a wireless market that, for years, was dominated by bipolar solutions. On wireless LAN and Bluethooth, RF CMOS is especially dominant, and it is becoming also in GSM cellular and GPS receivers. Hence, books that cover this widespread domain respond to a real need. The first edition of this book, published on 1998, was a pioneering textbook on the field of RF CMOS design. This second edition is a very interesting and upgraded version that includes new material and revised topics. In particular, it now includes a chapter on the fundamentals of wireless systems. The chapter on IC components is greatly expanded and now follows that on passive RLC components. The chapter on MOS devices has been updated since it includes the understanding of the model for the shorth-channel MOS and considers and discusses the scaling trends and its impact on the next several years. It has also expanded the topic of power amplifiers; indeed, it now also covers techniques for linearization and efficiency enhancement. Low-noise amplifiers, oscillators, and phase noise are now expanded and treated with more detail. Moreover, the chapter on transceiver architectures now includes much more detail, especially on direct-conversion architecture. Finally, additional commentary on practical details on simulations, floorplanning, and packaging has been added. The first edition of this book widely covered all the main arguments needed in the CMOS design context and provided a bridge between system and circuit issues. This second edition, which is upgraded and improved, is really useful, both in the industry and academia, for the new generation of RF engineers. Indeed, it is suited for students taking courses on RF design and is a valuable reference for practicing engineers. Of course, the arguments treated in the textbook lead up to low-frequency analog design IC topics. Hence, readers have to be intimately familiar with that subject. The book is divided into 20 chapters: 1) A Nonlinear History of Radio 2) Overview of Wireless Principles 3) Passive RLC Networks 4) Characteristics of Passive IC Components 5) A Review of MOS Device Physics; 6) Distributed Systems 7) The Smith Chart and S-Parameters 8) Bandwidth Estimation Techniques 9) High-Frequency Amplifier Design 10) Voltage References and Biasing 11) Noise 12) LNA Design 13) Mixers 14) Feedback Amplifiers 15) RF Power Amplifiers 16) Phase Locked Loop 17) Oscillators and Synthesizers 18) Phase Noise 19) Architectures 20) RF Circuits Through the Ages. Moreover, it contains over 100 circuit diagrams and many homework problems. Gaetano Palumbo
3,949 citations
"A 200PS differential CMOS delay ele..." refers methods in this paper
...For low pass filters, an approximation about delay can be made by using equation (9) [10]....
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10 Dec 1995
TL;DR: In this article, an aspect ratio of /spl sim/2 is proposed to increase the layout density and reduce the RC delay of ULSI interconnects, but at the expense of increased RC delay.
Abstract: Reducing interconnect pitch improves layout density, but degrades interconnect RC delay. Increasing metal aspect ratio (thickness/width) improves RC delay, but maximum benefits are achieved at an aspect ratio of /spl sim/2. Adding more interconnect layers improves density and performance, but practical limits are reached in just a few generations. New conductor and dielectric materials and improved circuit design techniques will be needed to meet future ULSI interconnect requirements.
555 citations
"A 200PS differential CMOS delay ele..." refers background in this paper
...Below 100nm, global interconnect delay exceeds gate delay [1] [2]....
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TL;DR: This is the first known demonstration of an on-chip clock transmitter with an integrated antenna and the second demonstration of a clock receiver with anIntegrated antenna, where the receiver's frequency and interconnection distance have approximately been doubled over previous results.
Abstract: A wireless interconnect system which transmits and receives RF signals across a chip using integrated antennas, receivers, and transmitters is proposed and demonstrated. The transmitter consists of a voltage-controlled oscillator, an output amplifier, and an antenna, while the receiver consists of an antenna, a low-noise amplifier, a frequency divider, and buffers. Using a 0.18-/spl mu/m CMOS technology, each of these individual circuits is demonstrated at 15 GHz. Wireless interconnection for clock distribution is then demonstrated in two stages. First, a wireless transmitter with integrated antenna generates and broadcasts a 15-GHz global clock signal across a 5.6-mm test chip, and this signal is detected using receiving antennas. Second, a wireless clock receiver with an integrated antenna detects a 15-GHz global clock signal supplied to an on-chip transmitting antenna located 5.6 mm away from the receiver, and generates a 1.875-GHz local clock signal. This is the first known demonstration of an on-chip clock transmitter with an integrated antenna and the second demonstration of a clock receiver with an integrated antenna, where the receiver's frequency and interconnection distance have approximately been doubled over previous results.
368 citations
Additional excerpts
...Using wireless interconnect is a viable approach towards solving these problems [3]....
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TL;DR: In this paper, a varactor-loaded transmission-line phase shifter using lumped elements is discussed and a monolithic-microwave integrated circuit (MMIC) is fabricated to verify the proposed topology.
Abstract: The design of varactor-loaded transmission-line phase shifters using lumped elements is discussed in this paper. A monolithic-microwave integrated-circuit (MMIC) phase shifter is fabricated to verify the proposed topology. Only one control voltage is required for phase control. Within a continuously adjustable phase-control range of 360/spl deg/ and a frequency range from 5 to 6 GHz, a low transmission loss of 4 dB/spl plusmn/1.7 dB is measured. The phase shifter is realized with a commercial 0.6-/spl mu/m GaAs MESFET process and requires a chip area of only 0.8 mm/sup 2/. To the knowledge of the authors, the best results reported to date are reached for a continuously adjustable passive phase shifter with comparable circuit size. The presented circuit is well suited to wireless adaptive antenna transceivers, operating in accordance with the 802.11a, high-performance radio local-area-network and high-speed wireless-access-network type-a standard.
173 citations
"A 200PS differential CMOS delay ele..." refers methods in this paper
...Most of the currently available designs for delay elements use Bucket Brigade Device [4], inverter chain [5], transmission line [6] or low pass LC filter network [7][8]....
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01 Mar 1982
86 citations
"A 200PS differential CMOS delay ele..." refers background in this paper
...Three differential delay stages with characteristics impedance of 100 Ω are cascades to build the 200 ps delay element....
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...A single ended implementation of the circuit having mentioned transfer function is given in [9]....
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