Proceedings ArticleDOI
A 20Gbps on-chip transceiver with equalization technique for global signal transmission
Wei Mo,Keng Chen,Yi Liu,Qi Wang +3 more
- pp 1-4
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TLDR
Current Mode Logic transmitter and Continuous-Time Linear Equalizer are adopted to reduce the impact of line loss and inter-symbol interference (ISI) in long interconnection of Network on Chip (NoC).Abstract:
In order to achieve high-speed and low-power signal transmission in long interconnection of Network on Chip (NoC), the performance of co-planar differential transmission line (DTL) is analyzed by HFSS in this paper Current Mode Logic (CML) transmitter and Continuous-Time Linear Equalizer (CTLE) are adopted to reduce the impact of line loss and inter-symbol interference (ISI) Simulation results by Spectre show that the transceiver can transmit 20Gbps data through 10mm DTL in 130nm standard CMOS process, the unit power is only 044pj/bitread more
Citations
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Journal ArticleDOI
Line-impedance matching and signal conditioning capabilities for high-speed feed-forward voltage-mode transmit drivers
TL;DR: This work presents the design and implementation of a power-efficient 2-tap feed-forward voltage mode driver which has impedance tuning and signal conditioning capabilities and has a robust mechanism to match its impedance to the line impedance even when signal conditioning is enabled which minimizes reflection and improves signal quality.
Proceedings ArticleDOI
7-mm low-latency inter-chiplet serial link with silicon interposer
TL;DR: This work introduces high-frequency inter-chip links and uses duobinary modulation to achieve higher bandwidth per channel, this modulation having the same spectral efficiency as PAM-4 without the need for extra comparators.
Proceedings ArticleDOI
A novel loss evaluation method for differential transmission lines
Ping Chen,Wei Mo,Yi Liu +2 more
TL;DR: A novel loss evaluating method considering coupling effects based on a parallel RLC differential transmission line (DTL) model in nanometer CMOS process is proposed, which enables the estimation of the loss within 6.48% average error compared with measured results.
2.56 Gbps CML transceiver for data concentrator ASIC
E. V. Atkin,A. R. Serazetdinov +1 more
TL;DR: The transceiver was designed as an interface part of the data concentrator ASIC, intended for the frontend electronics of the time-projection chamber of the MPD experiment at NICA nuclotron.
Journal ArticleDOI
2.56 Gbps CML transceiver for data concentrator ASIC
TL;DR: In this article , a CML transceiver was designed as an interface part of the data concentrator ASIC, intended for the front-end electronics of the time-projection chamber of the MPD experiment at NICA nuclotron.
References
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Proceedings ArticleDOI
High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS
TL;DR: This paper extends capacitive-mode signaling to a capacitively driven pulse-mode wire using a transmit-side adaptive FIR filter and a clockless receiver, and shows bandwidth densities of 2.2–4.4 Gb/s/µm over 90nm 5mm links.
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A 9-Gbit/s Serial Transceiver for On-Chip Global Signaling Over Lossy Transmission Lines
TL;DR: A 9-Gbit/s serial link transceiver for on-chip global signaling, and techniques for the design of on- chip transmission lines, are presented.
Journal ArticleDOI
Using Transmission Lines for Global On-Chip Communication
TL;DR: This paper will provide a design of such a system from the ground up, including design of the transmission lines, transceiver circuits, and a simple, yet effective, architectural design for a shared-medium interconnect, and show that such a design can be a compelling alternative to packet-switched networks for CMPs.
Proceedings ArticleDOI
A 6.5-mW 5-Gbps On-Chip Differential Transmission Line Interconnect with a Low-Latency Asymmetric Tx in a 180nm CMOS Technology
TL;DR: In this paper, an on-chip differential transmission-line (DTL) interconnect is proposed to reduce delay and power consumption in long global interconnects, which can transmit signals at near light-of-speed with small power dissipation of Tx.
Proceedings ArticleDOI
Design methodology of high performance on-chip global interconnect using terminated transmission-line
Yulei Zhang,Ling Zhang,Alina Deutsch,George A. Katopis,Daniel M. Dreps,James F. Buckwalter,Ernest S. Kuh,Chung-Kuan Cheng +7 more
TL;DR: The proposed T-line schemes reduce the delay and improve the throughput as much as 82% and 63%, for min-ddp (delay2-power product) objective, and design methodology is proposed to determine the optimal design variables for three objectives.