A 256/spl times/256 CMOS imaging array with wide dynamic range pixels and column-parallel digital output
05 Feb 1998-Vol. 33, Iss: 12, pp 2081-2091
TL;DR: A 256x256 CMOS active pixel sensor (APS) is described for an automotive stereo-vision system that simultaneously provides flexibility, user-adjustability, and digital control, with no reduction of fill factor.
Abstract: A 256x256 CMOS active pixel sensor (APS) is described for an automotive stereo-vision system. Illumination may vary over several orders of magnitude, requiring a high dynamic range imager. Dynamic range is increased 20/spl times/ using a special clocking scheme for the lateral overflow gate. This dynamic range enhancement offers improvements over previously-described techniques. It simultaneously provides flexibility, user-adjustability, and digital control, with no reduction of fill factor. On-chip column-parallel cyclic analog-to-digital converters (ADCs) produce digital output at frame rates from 30 to 390 frames/s.
Citations
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TL;DR: This article provides a basic introduction to CMOS image-sensor technology, design and performance limits and presents recent developments and future research directions enabled by pixel-level processing, which promise to further improveCMOS image sensor performance and broaden their applicability beyond current markets.
Abstract: In this article, we provide a basic introduction to CMOS image-sensor technology, design and performance limits and present recent developments and future directions in this area. We also discuss image-sensor operation and describe the most popular CMOS image-sensor architectures. We note the main non-idealities that limit CMOS image sensor performance, and specify several key performance measures. One of the most important advantages of CMOS image sensors over CCDs is the ability to integrate sensing with analog and digital processing down to the pixel level. Finally, we focus on recent developments and future research directions that are enabled by pixel-level processing, the applications of which promise to further improve CMOS image sensor performance and broaden their applicability beyond current markets.
748 citations
Cites methods from "A 256/spl times/256 CMOS imaging ar..."
...To solve this problem, several DR extension techniques such as well-capacity adjusting [15], multiple capture [18], time-to-saturation [36], and self-reset [37] have been proposed....
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...The reset transistor can also be used to enhance DR via well capacity adjusting, as described in [15]....
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TL;DR: The biomimetic CMOS dynamic vision and image sensor described in this paper is based on a QVGA array of fully autonomous pixels containing event-based change detection and pulse-width-modulation imaging circuitry, which ideally results in lossless video compression through complete temporal redundancy suppression at the pixel level.
Abstract: The biomimetic CMOS dynamic vision and image sensor described in this paper is based on a QVGA (304×240) array of fully autonomous pixels containing event-based change detection and pulse-width-modulation (PWM) imaging circuitry. Exposure measurements are initiated and carried out locally by the individual pixel that has detected a change of brightness in its field-of-view. Pixels do not rely on external timing signals and independently and asynchronously request access to an (asynchronous arbitrated) output channel when they have new grayscale values to communicate. Pixels that are not stimulated visually do not produce output. The visual information acquired from the scene, temporal contrast and grayscale data, are communicated in the form of asynchronous address-events (AER), with the grayscale values being encoded in inter-event intervals. The pixel-autonomous and massively parallel operation ideally results in lossless video compression through complete temporal redundancy suppression at the pixel level. Compression factors depend on scene activity and peak at ~1000 for static scenes. Due to the time-based encoding of the illumination information, very high dynamic range - intra-scene DR of 143 dB static and 125 dB at 30 fps equivalent temporal resolution - is achieved. A novel time-domain correlated double sampling (TCDS) method yields array FPN of 56 dB (9.3 bit) for >10 Lx illuminance.
632 citations
Cites background from "A 256/spl times/256 CMOS imaging ar..."
...While some designs use either variable integration times or time-dependent well capacities to increase dynamic range [19]–[21], other designs are based on directly measuring the time it takes the photocurrent to produce a given voltage change at the sense node....
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TL;DR: In this paper, a detailed and rigorous analysis of temporal noise due to thermal and shot noise sources in CMOS active pixel sensor (APS) is presented, which takes into consideration the time-varying circuit models, the fact that the reset transistor operates in subthreshold during reset, and the nonlinearity of the charge to voltage conversion, which is becoming more pronounced as CMOS technology scales.
Abstract: Temporal noise sets the fundamental limit on image sensor performance, especially under low illumination and in video applications. In a CCD image sensor, temporal noise is primarily due to the photodetector shot noise and the output amplifier thermal and 1/f noise. CMOS image sensors suffer from higher noise than CCDs due to the additional pixel and column amplifier transistor thermal and 1/f noise. Noise analysis is further complicated by the time-varying circuit models, the fact that the reset transistor operates in subthreshold during reset, and the nonlinearity of the charge to voltage conversion, which is becoming more pronounced as CMOS technology scales. The paper presents a detailed and rigorous analysis of temporal noise due to thermal and shot noise sources in CMOS active pixel sensor (APS) that takes into consideration these complicating factors. Performing time-domain analysis, instead of the more traditional frequency-domain analysis, we find that the reset noise power due to thermal noise is at most half of its commonly quoted kT/C value. This result is corroborated by several published experimental data including data presented in this paper. The lower reset noise, however, comes at the expense of image lag. We find that alternative reset methods such as overdriving the reset transistor gate or using a pMOS transistor can alleviate lag, but at the expense of doubling the reset noise power. We propose a new reset method that alleviates lag without increasing reset noise.
411 citations
Cites background or methods from "A 256/spl times/256 CMOS imaging ar..."
...As technology scales or when employing certain high dynamic range schemes [ 7 ], the nonlinearity effects on SNR cannot be ignored....
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...Hand analysis of the noise in CCDs and CMOS APS have been published by several authors [1]‐[ 7 ]....
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TL;DR: In this article, an Arbitrated address-event imager was designed and fabricated in a 0.6-/spl mu/m CMOS process, which is composed of 80 /spl times/ 60 pixels of 32 /spltimes/ 30 /spl m/m. Tests conducted on the imager showed a large output dynamic range of 180 dB (under bright local illumination) for an individual pixel.
Abstract: An arbitrated address-event imager has been designed and fabricated in a 0.6-/spl mu/m CMOS process. The imager is composed of 80 /spl times/ 60 pixels of 32 /spl times/ 30 /spl mu/m. The value of the light intensity collected by each photosensitive element is inversely proportional to the pixel's interspike time interval. The readout of each spike is initiated by the individual pixel; therefore, the available output bandwidth is allocated according to pixel output demand. This encoding of light intensities favors brighter pixels, equalizes the number of integrated photons across light intensity, and minimizes power consumption. Tests conducted on the imager showed a large output dynamic range of 180 dB (under bright local illumination) for an individual pixel. The array, on the other hand, produced a dynamic range of 120 dB (under uniform bright illumination and when no lower bound was placed on the update rate per pixel). The dynamic range is 48.9 dB value at 30-pixel updates/s. Power consumption is 3.4 mW in uniform indoor light and a mean event rate of 200 kHz, which updates each pixel 41.6 times per second. The imager is capable of updating each pixel 8.3K times per second (under bright local illumination).
362 citations
Additional excerpts
...integration time of each pixel based on the light intensity [13]....
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15 Feb 1999
TL;DR: A 640/spl times/512 image sensor with Nyquist rate pixel level ADC implemented in a 0.35 /spl mu/m CMOS technology shows how a pixellevel ADC enables flexible efficient implementation of multiple sampling.
Abstract: Analysis results demonstrate that multiple sampling can achieve consistently higher signal-to-noise ratio at equal or higher dynamic range than using other image sensor dynamic range enhancement schemes such as well capacity adjusting. Implementing multiple sampling, however, requires much higher readout speeds than can be achieved using typical CMOS active pixel sensor (APS). This paper demonstrates, using a 640/spl times/512 CMOS image sensor with 8-b bit-serial Nyquist rate analog-to-digital converter (ADC) per 4 pixels, that pixel-level ADC enables a highly flexible and efficient implementation of multiple sampling to enhance dynamic range. Since pixel values are available to the ADC's at all times, the number and timing of the samples as well as the number of bits obtained from each sample can be freely selected and read out at fast SRAM speeds. By sampling at exponentially increasing exposure times, pixel values with binary floating-point resolution can be obtained. The 640/spl times/512 sensor is implemented in 0.35-/spl mu/m CMOS technology and achieves 10.5/spl times/10.5 /spl mu/m pixel size at 29% fill factor. Characterization techniques and measured quantum efficiency, sensitivity, ADC transfer curve, and fixed pattern noise are presented. A scene with measured dynamic range exceeding 10000:1 is sampled nine times to obtain an image with dynamic range of 65536:1. Limits on achievable dynamic range using multiple sampling are presented.
345 citations
Cites background or methods from "A 256/spl times/256 CMOS imaging ar..."
...In [ 1 ], the dynamic range of a CMOS active pixel sensor (APS) is enhanced by increasing well capacity one or more times during...
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...The well capacity adjusting scheme described by Knight [2] and Sayag [3] and implemented by Decker [ 1 ] compresses the sensor’s current versus charge response curve using a lateral overflow gate, e.g., the reset transistor gate in a CMOS APS....
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...An important advantage of this scheme, over other dynamic range enhancement schemes [ 1 ], is that the combined digital output is linear in illumination....
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References
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TL;DR: In this article, the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed.
Abstract: CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed.
1,182 citations
"A 256/spl times/256 CMOS imaging ar..." refers methods in this paper
...Several approaches have been taken to focal-plane data conversion, including sigma‐delta, successive approximation, and single-slope architectures [13]‐[ 15 ]....
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TL;DR: An algorithmic analog-to-digital conversion technique is described which is capable of achieving high-resolution conversion without the use of matched capacitors in an MOS technology.
Abstract: An algorithmic analog-to-digital conversion technique is described which is capable of achieving high-resolution conversion without the use of matched capacitors in an MOS technology. The exact integral multiplication of the signal required by the conversion is realized through an algorithmic circuit method which involves charge summing with an MOS integrator and exchange of capacitors. A first-order cancellation of the charge injection effect from MOS transistor switches is attained with a combination of differential circuit implementation and an optimum timing scheme. An experimental prototype has been fabricated with a standard 5-/spl mu/m n-well CMOS process. It achieves 12-bit resolution at a sampling rate of 8 kHz. The analog chip area measures 2400 mils/SUP 2/.
325 citations
Book•
01 Jan 1975
TL;DR: It is projected that charge transfer devices will rapidly find their way into certain analog delay, image sensing, and digital applications.
Abstract: This is a review describing the use of charge transfer devices for digital memory, analog delay, and image sensing. Short descriptions of different types of charge-coupled devices and MOS bucket-brigade devices are presented. Those factors such as transfer inefficiency, noise, and dark current which affect the performance of these devices in the above applications are discussed. Various possible organizations of charge transfer devices to serve different functions are described. Many charge transfer devices have been fabricated and already indicate a high degree of achievement. Transfer inefficiencies per transfer in the range 10−3 to 10−4 have been measured. Finally, it is projected that charge transfer devices will rapidly find their way into certain analog delay, image sensing, and digital applications.
257 citations
08 Feb 1996
TL;DR: In this paper, an active pixel sensor (APS) is integrated on a CMOS chip with the timing and control circuits, and signal conditioning to enable random access, low power (/spl sim/5 mW) operation, and low read noise (13 e/sup -/ rms).
Abstract: A CMOS imaging sensor is described that uses active pixel sensor (APS) technology and permits the integration of the detector array with on-chip timing, control, and signal chain electronics. This sensor technology has been used to implement a CMOS APS camera-on-a-chip. The camera-on-a-chip features a 256/spl times/256 APS sensor integrated on a CMOS chip with the timing and control circuits, and signal-conditioning to enable random-access, low power (/spl sim/5 mW) operation, and low read noise (13 e/sup -/ rms). The chip features simple power supplies, fast readout rates, and a digital interface for commanding the sensor, as well as for programming the window-of-interest readout and exposure times. Excellent imaging has been demonstrated with the APS camera-on-a-chip, and the measured performance indicates that this technology will be competitive with charge-coupled devices (CCD's) in many applications.
256 citations