A 3.3 V, 8.89 μA and 5.5 ppm/°C CMOS bandgap voltage reference for power telemetry in retinal prosthesis systems
01 Jul 2018-Vol. 2018, pp 2977-2980
TL;DR: A 3.3 V CMOS bandgap reference (BGR) was presented in this study that utilizes MOS transistors operating in the sub-threshold region and the complexity of the circuit and the dependency of the voltage reference on power supply variations are simultaneously decreased through the use of a new compensation circuit technique.
Abstract: A 3.3 V CMOS bandgap reference (BGR) was presented in this study that utilizes MOS transistors operating in the sub-threshold region. The complexity of the circuit and the dependency of the voltage reference on power supply variations are simultaneously decreased through the use of a new compensation circuit technique. The proposed BGR is simulated using a 0.35 $\mu \mathrm{m}$ CMOS standard process. Consequently, a 5.53 ppm/°C temperature coefficient is obtained in the -40~+125 °C temperature range, the maximum power supply rejection ratio is - 62 dB, and a 2.033 mV/V voltage line regulation is achieved for the $2.3\sim 4.3$ V supply voltage. The proposed circuit dissipates a supply current of 8.89 IJA at a 3.3 V supply voltage, and the active area is 112 $\mu \mathrm{m}\times 60 \mu \mathrm{m}$.
Citations
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01 Oct 2019
TL;DR: In this article, an improved piecewise curvature-corrected bandgap voltage reference (BGR) with low temperature coefficient and better line regulation was designed in the CMOS process.
Abstract: Voltage reference circuit play a vital role in analog circuits. A reference voltage is expected to be high precision and insensitive to power supply, process and temperature variation. An improved piecewise curvature-corrected bandgap voltage reference (BGR) with low temperature coefficient and better line regulation was designed in this research work. The proposed BGR consisting of piecewise curvature-corrected circuit was implemented in $0.18-\mu \mathrm{m}$ CMOS process. At DC supply of 1.8 V, the piecewise curvature-corrected BGR can function properly with output reference voltage of 549.0 mV to 550.2 mV by varying supply voltage of 1.8 V to 3.0 V. The best temperature coefficient that can be achieved is 3.83 ppm/ °C with temperature of $-25^{\circ}\mathrm{C}$ to $70^{\circ}\mathrm{C}$ at a supply voltage of 1.8 V. The proposed piecewise curvature-corrected bandgap voltage reference is able to function properly with high precision, which is ready to be fabricated. It is suitable module for applications such as ADC, DAC, voltage regulators and PLL.
References
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TL;DR: A method for developing a reference voltage in CMOS integrated circuits is described, and the principle of the suggested voltage reference is explained and the final implementation is presented.
Abstract: A method for developing a reference voltage in CMOS integrated circuits is described. The circuit uses MOS devices operating in the weak inversion region, as well as a bipolar device formed without process modifications. A brief description of this region of operation is given. Then, the principle of the suggested voltage reference is explained and the final implementation is presented. Higher order effects are discussed, and results from an integrated prototype given.
156 citations
"A 3.3 V, 8.89 μA and 5.5 ppm/°C CMO..." refers background in this paper
...(6) Previous work corroborated that parameter n in (6) is not constant; the detailed explanation of the MOSFET behavioral as a temperature function is described in [10]....
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TL;DR: A novel CMOS bandgap reference with high-order curvature-compensation by using MOS transistors operating in weak inversion region using standard CMOS 0.18 μm technology is proposed, suitable for low-power applications requiring references with high precision.
Abstract: This paper proposes a novel CMOS bandgap reference (BGR) with high-order curvature-compensation by using MOS transistors operating in weak inversion region. The mechanism of the proposed curvature-compensation technique is analyzed thoroughly and the corresponding BGR circuit was implemented in standard CMOS 0.18 μm technology. The experimental results show that the proposed BGR achieves 4.5 ppm/°C over the temperature range of -40°C to 120°C at 1.2 V supply voltage. It consumes only 36 μA. In addition, it achieves line regulation performance of 0.054%/V. It is suitable for low-power applications requiring references with high precision.
117 citations
"A 3.3 V, 8.89 μA and 5.5 ppm/°C CMO..." refers background or methods or result in this paper
...The overall performance of the proposed BGR at the typical condition is tabulated in Table 1 in which it is also compared with the previous bandgap voltage reference circuit [5] and [6] ....
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...The drain current of NMOS operating in this region is given by [6]...
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...Significant outstanding works for BGR design have recently been conducted, and among them, the curvature-corrected technique [5, 6, 7] has been widely employed to significantly reduce voltage variation in a wide temperature range....
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...ELECTRICAL PARAMETERS Parameter This work [5] [6] Technology CMOS 0....
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TL;DR: In this paper, a bandgap-voltage reference implemented with a new accurate circuit configuration for compensating the thermal nonlinearity of the base-emitter voltage is described, achieving a temperature coefficient of 0.5 ppm/spl deg/C over the temperature range -25 to +85/spl/C.
Abstract: A bandgap-voltage reference implemented with a new accurate circuit configuration for compensating the thermal nonlinearity of the base-emitter voltage is described. With this device, a temperature coefficient of 0.5 ppm//spl deg/C over the temperature range -25 to +85/spl deg/C has been achieved. The minimum required supply voltage amounts to only 5.5 V.
86 citations
TL;DR: The central component of an electrical retinal prosthesis is a wirelessly powered and driven stimulator chip that receives commands from the outside and outputs biphasic current pulses to an electrode array placed in the retina that stimulate the remaining retinal neurons.
Abstract: Retinal prostheses are being developed around the world in hopes of restoring useful vision for patients suffering from certain types of diseases like age-related macular degeneration (AMD) and retinitis pigmentosa. The central component of an electrical retinal prosthesis is a wirelessly powered and driven stimulator chip. The chip receives commands from the outside and outputs biphasic current pulses to an electrode array placed in the retina that stimulate the remaining retinal neurons. The chip contains 30\thinspace000 transistors in a 0.5 mum technology (two-poly three-metal, 2P3M), occupies an area of 2.3 mm x 2.3 mm, and excluding the current sources consumes less than 2 mW of power. The chip is powered inductively via a 125 kHz power signal which is rectified to generate a plusmn2.5nV supply. The data signal is transmitted as an amplitude shift keyed (ASK) signal on a 13.56 MHz carrier. The data rate can be varied from 25 to 714 kHz and the symbol (0 or 1) is encoded as the pulse width of the data signal. A self-biased feedback-loop-based single-to-differential converter restores the signal to full rail levels. Clock and data recovery is performed by a self-biased low-power inverter-based delay-locked loop (DLL). The chip can receive four commands, and each command is 16 bits long. The current amplitude, pulse duration, and inter-pulse duration can be programmed by using the four commands.
81 citations
"A 3.3 V, 8.89 μA and 5.5 ppm/°C CMO..." refers background in this paper
...A retinal prosthetic for restoring visual function loss is one current and representative example of such implantable systems utilizing short-distance wireless communication [2]....
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TL;DR: A fully intraocular self-calibrating epiretinal prosthesis with 512 independent channels in 65 nm CMOS with a novel digital calibration technique that matches the biphasic currents of each channel independently while the calibration circuitry is shared among every 4 channels.
Abstract: This paper presents a fully intraocular self-calibrating epiretinal prosthesis with 512 independent channels in 65 nm CMOS. A novel digital calibration technique matches the biphasic currents of each channel independently while the calibration circuitry is shared among every 4 channels. Dual-band telemetry for power and data with on-chip rectifier and clock recovery reduces the number of off-chip components. The rectifier utilizes unidirectional switches to prevent reverse conduction loss in the power transistors and achieves an efficiency > 80%. The data telemetry implements a phase-shift keying (PSK) modulation scheme and supports data rates up to 20 Mb/s. The system occupies an area of 4.5 ×3.1 mm2. It features a pixel size of 0.0169 mm2 and arbitrary waveform generation per channel. In vitro measurements performed on a Pt/Ir concentric bipolar electrode in phosphate buffered saline (PBS) are presented. A statistical measurement over 40 channels from 5 different chips shows a current mismatch with μ = 1.12 μA and σ = 0.53 μA. The chip is integrated with flexible MEMS origami coils and parylene substrate to provide a fully intraocular implant.
78 citations
"A 3.3 V, 8.89 μA and 5.5 ppm/°C CMO..." refers background in this paper
...the biphasic pulse should be balanced to avoid the accumulation of electrical charge on electrodes, which may result in tissue damage [4]....
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