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Journal ArticleDOI

A 3-D Analytical Physically Based Model for the Subthreshold Swing in Undoped Trigate FinFETs

TL;DR: An analytical physically based analysis for undoped FinFET devices in the subthreshold and near-threshold regimes has been developed by solving the 3-D Poisson equation, in which the mobile-charge term was included as mentioned in this paper.
Abstract: An analytical physically based analysis for undoped FinFET devices in the subthreshold and near-threshold regimes has been developed by solving the 3-D Poisson equation, in which the mobile-charge term was included. From this analysis, a subthreshold-swing model has been developed; this model is also based on a new physically based analysis of the conduction path. The subthreshold-swing model has been verified by comparison with 3-D numerical simulations and measured values; a very good agreement with both 3-D numerical simulation and the experimental results was observed.
Citations
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Journal ArticleDOI
01 Aug 2009
TL;DR: This paper reviews recent development on compact modeling of multiple-gate (MG) MOSFETs and finds that by adding quantum mechanical effects and short-channel effects, the core model has been expanded into a full-blown compact model which has been calibrated to and validated by experimental FinFET hardware.
Abstract: This paper reviews recent development on compact modeling of multiple-gate (MG) MOSFETs. Long-channel core models based on the analytical potential solutions of Poisson and current continuity equations for symmetric double-gate (DG) and surrounding-gate (SG) MOSFETs have been developed first. Highly accurate explicit solutions are subsequently developed to deal with the implicit algebraic equations of the models. By adding quantum mechanical effects and short-channel effects, as well as capacitance formulations, the core model for DG MOSFETs has been expanded into a full-blown compact model which has been calibrated to and validated by experimental FinFET hardware. With regard to the various other types of MG MOSFETs developed, the core models for DG and SG MOSFETs have been generalized to the less symmetric structures, including quadruple-gate (QG), triple-gate (TG), ?-gate, and ?-gate MOSFETs. Other research activities on multiple-gate MOSFETs are briefly summarized at the end.

76 citations


Cites background from "A 3-D Analytical Physically Based M..."

  • ...Short-channel effects [32], [33] and quantum mechanical effects [34], [35] have been modeled, so have body doping [36], [37] and corner effects [38]....

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Journal ArticleDOI
TL;DR: In this article, a 3D analytical modeling of SOI multigate (GAA), triple-gate (TG), double-gate and double-Gate (DG) FinFETs is presented.

71 citations

Journal ArticleDOI
TL;DR: In this paper, a simple analytical expression of the 3D potential distribution along the channel of lightly doped silicon trigate MOSFETs in weak inversion is derived, based on a perimeter-weighted approach of symmetric and asymmetric double-gate MOSFLETs.
Abstract: A simple analytical expression of the 3-D potential distribution along the channel of lightly doped silicon trigate MOSFETs in weak inversion is derived, based on a perimeter-weighted approach of symmetric and asymmetric double-gate MOSFETs. The analytical solution is compared with the numerical solution of the 3-D Poisson's equation in the cases where the ratios of channel length/silicon thickness and channel length/channel width are ges 2. Good agreement is achieved at different positions within the channel. The perimeter-weighted approach fails at the corner regions of the silicon body; however, by using corner rounding and undoped channel to avoid corner effects in simulations, the agreement between model and simulation results is improved. By using the extra potential induced in the silicon film due to short-channel effects, the subthreshold drain current is determined in a semianalytical way, from which the subthreshold slope, the drain-induced barrier lowering, and the threshold voltage are extracted.

67 citations


Cites methods from "A 3-D Analytical Physically Based M..."

  • ...Recently, the analytical solution of the 3-D Poisson’s equation in undoped FinFETs resulted in a rather complicated semianalytical expression for the 3-D electrostatic potential, since the 1-D potential distribution along the silicon thickness requires numerical calculation [22]....

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  • ...Thus, instead of solving the 3-D Poisson’s equation, which leads to a semianalytical expression for the potential distribution in TG MOSFETs [22], the potential Φ(x, y, z) can be accurately described with a simple analytical expression using a dimension-based approximation; the potential Φ(x, y, z) can be considered as the perimeter-weighted sum of the physically based potential distributions Φasym(x, y) and Φsym(y, z) due to the asymmetric and symmetric DG MOSFETs, respectively....

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Journal ArticleDOI
TL;DR: An analytical drain current model for undoped (or lightly doped) short-channel triple-gate fin-shaped field effect transistors (finFETs) is presented in this article.
Abstract: An analytical compact drain current model for undoped (or lightly doped) short-channel triple-gate fin-shaped field-effect transistors (finFETs) is presented, taking into account quantum-mechanical and short-channel effects such as threshold-voltage shifts, drain-induced barrier lowering, and subthreshold slope degradation. In the saturation region, the effects of series resistance, surface roughness scattering, channel length modulation, and saturation velocity were also considered. The proposed model has been validated by comparing the transfer and output characteristics with device simulations and with experimental results. The good accuracy and the symmetry of the model make it suitable for implementation in circuit simulation tools.

51 citations

Journal ArticleDOI
TL;DR: In this paper, an analytical approach for modeling the electrostatic potential in nanoscale undoped FinFETs is derived, which uses a 2D solution for this potential within a double-gate FET and takes into account the top gate electrode as the third dimension by applying the conformal mapping technique.
Abstract: An analytical approach for modeling the electrostatic potential in nanoscale undoped FinFETs is derived. This method uses a 2-D solution for this potential within a double-gate FET and takes into account the top gate electrode as the third dimension by applying the conformal mapping technique. Herewith, an analytical closed-form model for the height of the potential barrier below threshold is defined which includes 3-D effects. From that, models for subthreshold slope and threshold voltage of nanoscale triple-gate FETs are derived. The results are in good agreement with numerical device simulation results and measurements for channel lengths down to 20 nm.

47 citations


Cites background or methods from "A 3-D Analytical Physically Based M..."

  • ...2006535 the potential in triple-gate FETs, whose overview can be found in [4]....

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  • ...On the other hand, in [4] and [5], the influence of a back-gate bias is taken into account....

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  • ...However, the solution in [4] takes into account a mobile-charge term, making the approach interesting for the near-threshold regime of undoped devices....

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  • ..., if the channel thickness is less than the channel length, this series can be approximated by its first terms [2], [4]–[6]....

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  • ...The approaches presented in [2], [5], and [6] solve the 3-D potential in a volume, including the channel region and the gate oxide, whereas in [4], the potential is solved only in the silicon channel while applying boundary conditions at the silicon-to-oxide interface derived from 1-D analysis....

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References
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Journal ArticleDOI
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Abstract: MOSFETs with gate length down to 17 nm are reported To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed By using boron-doped Si/sub 04/Ge/sub 06/ as a gate material, the desired threshold voltage was achieved for the ultrathin body device The quasiplanar nature of this new variant of the vertical double-gate MOSFETs can be fabricated relatively easily using the conventional planar MOSFET process technologies

1,668 citations


"A 3-D Analytical Physically Based M..." refers background in this paper

  • ...So far, very little work has been done on the analytical modeling of FinFET devices, although there have been some works studying the FinFET performance through numerical simulation [6], or studying the device physics from experimental data [8]–[18]....

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Journal ArticleDOI
TL;DR: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion as discussed by the authors.
Abstract: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion. This original method of transistor operation offers excellent device performance, in particular great increases in subthreshold slope, transconductance, and drain current. A simulation program and experiments on SIMOX structures are used to study the new device.

729 citations


"A 3-D Analytical Physically Based M..." refers background in this paper

  • ...Due to this relatively even spreading of free electrons, known as volume inversion [22], the overall conduction yc is not confined to the channel center, and the effective conducting path should be somewhere in-between the surfaces and the channel center....

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Proceedings ArticleDOI
01 Jan 2002
TL;DR: In this paper, the authors report the design, fabrication, performance, and integration issues of double-gate FinFETs with the physical gate length being aggressively shrunk down to 10 nm and the fin width down to 12 nm.
Abstract: While the selection of new "backbone" device structure in the era of post-planar CMOS is open to a few candidates, FinFET and its variants show great potential in scalability and manufacturability for nanoscale CMOS In this paper we report the design, fabrication, performance, and integration issues of double-gate FinFETs with the physical gate length being aggressively shrunk down to 10 nm and the fin width down to 12 nm These MOSFETs are believed to be the smallest double-gate transistors ever fabricated Excellent short-channel performance is observed in devices with a wide range of gate lengths (10/spl sim/105 nm) The observed short-channel behavior outperforms any reported single-gate silicon MOSFETs Due to the [110] channel crystal orientation, hole mobility in the fabricated p-channel FinFET exceeds greatly that in a traditional planar MOSFET At 105 nm gate length, the p-channel FinFET shows a record-high transconductance of 633 /spl mu/S//spl mu/m at a V/sub dd/ of 12 V Working CMOS FinFET inverters are also demonstrated

611 citations

Proceedings ArticleDOI
01 Dec 1999
TL;DR: In this article, a self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect, and a 45 nm gate-length PMOS FinEET is presented.
Abstract: High performance PMOSFETs with gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. A 45 nm gate-length PMOS FinEET has an I/sub dsat/ of 410 /spl mu/A//spl mu/m (or 820 /spl mu/A//spl mu/m depending on the definition of the width of a double-gate device) at Vd=Vg=1.2 V and Tox=2.5 nm. The quasi-planar nature of this variant of the double-gate MOSFETs makes device fabrication relatively easy using the conventional planar MOSFET process technologies. Simulation shows possible scaling to 10-nm gate length.

550 citations


"A 3-D Analytical Physically Based M..." refers methods in this paper

  • ...P-channel FinFETs were subsequently demonstrated using a similar fabrication process and showed excellent characteristics [5]....

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Journal ArticleDOI
G. Pei1, J. Kedzierski2, P. Oldiges2, Meikei Ieong2, Edwin C. Kan1 
TL;DR: In this article, the authors investigated the design of the FinFET by 3D simulation and analytical modeling, and derived the threshold voltage (V/sub th/) rolloff and the subthreshold swing (S) by considering the source barrier changes in the most leaky channel path.
Abstract: Design considerations of the FinFET have been investigated by three-dimensional (3-D) simulation and analytical modeling in this paper. Short-channel effects (SCE) of the FinFET can be reasonably controlled by reducing either silicon fin height or fin thickness. Analytical solution of 3-D Laplace's equation is employed to establish the design equations for the subthreshold behavior in the fully depleted silicon fins. Based on the 3-D analytical electrostatic potential in the subthreshold region, the threshold voltage (V/sub th/) roll-off and the subthreshold swing (S) are estimated by considering the source barrier changes in the most leaky channel path. V/sub th/ roll-off is an exponential function of the ratio of effective channel length to drain potential decay length, which can then be expressed as a function of the fin thickness, the fin height and the gate oxide thickness. The drain-potential decay lengths of single-gate fully depleted SOI MOSFET (FDFET), double-gate MOSFET (DGFET), rectangular surrounding-gate MOSFET (SGFET), and FinFET are compared. The drain potential scaling length and V/sub th/ roll-off can be included into a universal relation for convenient comparison.

297 citations


"A 3-D Analytical Physically Based M..." refers background in this paper

  • ...[19] presented 3-D subthreshold swing and threshold-voltage rolloff models but are only valid for doped FinFET devices, i....

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