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Proceedings ArticleDOI

A 30 to 44 GHz divide-by-2, quadrature, direct injection locked frequency divider for sliding-IF 60 GHz transceivers

01 Mar 2010-pp 57-60

AbstractThis paper presents a wideband 40 GHz divide-by-2 quadrature injection locked frequency divider (Q-ILFD) as an enabling component for sliding-IF 60 GHz transceivers. The design incorporates direct injection topology and input power matching using interconnect inductances to enhance injection efficiency. This results in an excellent input sensitivity and a wide locking range. Fabricated in a 65nm bulk CMOS technology, the divider operates from 30.3 to 44 GHz (37% locking range) while consuming 9mW from a 1.2V supply. The measured phase noise is −131 dBc/Hz at 1-MHz offset whereas the phase error between I-Q outputs is less than 1.44°.

Topics: Frequency divider (66%), Frequency multiplier (57%), Frequency synthesizer (55%), Phase noise (53%), CMOS (51%)

Summary (1 min read)

INTRODUCTION

  • The availability of high f T silicon IC technologies capable of operating at millimeter wave (mm-wave) frequencies and the extraordinary interest for high data rate (>1Gbps) applications has motivated research and development of 60 GHz transceivers in recent years.
  • Therefore, alternative synthesizer friendly architectures based on double-heterodyne, sliding-IF, low-IF and half-RF architectures are being investigated.
  • On the other hand, injection locked frequency dividers can operate at very high frequencies but are inherently narrowband due to their LC-tanks.
  • The first mixing operation with the VCO transfers the RF signal from 60 GHz to 20 GHz.
  • Section II describes the circuit design of the ILFD, followed by a brief discussion, in section III, about layout and technology used.

II. THEORY AND CIRCUIT DESIGN

  • In conventional ILFD's the RF input signal is injected at the common-source node of the oscillator which is inherently running at double the fundamental frequency.
  • Therefore, the need of quadrature outputs, especially for the system in Fig. 1 , is naturally felt.
  • The coupling, called parallel or anti-phase coupling, is achieved by connecting one ILFD output to the other ILFD with transistors M7-M10 in parallel to the cross coupled transistors M1, M2 and M4, M5.
  • The injection transistors M3 and M6 are 9µm wide with minimum channel length.
  • Due to capacitive input of the injection transistors, there is an inherent power mismatch between the gate input and the signal generator equipment.

III. LAYOUT AND TECHNOLOGY

  • The layout of the divider is done carefully and compactly to reduce unnecessary parasitics.
  • The RF signal paths between the tank and negative gm-cells are kept short and narrow lines are avoided to reduce resistive losses.
  • The coupling transistors (M7-M10) are perfectly matched to ensure identical oscillation frequencies for both stages.
  • These TLs are coplanar waveguide based with lateral ground plane consisting of all metal layers "sandwiched" together using large of vias, thus providing excellent noise isolation.
  • The dividers are fabricated in TSMC bulk CMOS 65nm LP (low-power) process having six metallization layers.

IV. MEASUREMENT RESULTS

  • The input 40 GHz signal from an Agilent signal generator is applied to a single-to-differential converter (180° hybrid) and then passed on the RF probe.
  • Similarly, input sensitivity for different varactor tuning voltage is measured, three of which are plotted in Fig. 6 .
  • The improved injection efficiency due to direct injection topology and input power matching technique, results in the required input power close to free-running frequency of the ILFD to be as low as -38 dBm.
  • The phase noise variation over the complete operating range is + 2.5 dB.
  • The output buffers used for measurement purpose consume 12mW.

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A 30 to 44 GHz Divide-by-2, Quadrature, Direct
Injection Locked Frequency Divider for Sliding-IF
60 GHz Transceivers
Hammad M. Cheema, Reza Mahmoudi, Arthur van Roermund
Department of Electrical Engineering, Mixed-signal Microelectronics group,
Eindhoven University of Technology, 5600 MB,
Eindhoven, The Netherlands
AbstractThis paper presents a wideband 40 GHz divide-by-2
quadrature injection locked frequency divider (Q-ILFD) as an
enabling component for sliding-IF 60 GHz transceivers. The
design incorporates direct injection topology and input power
matching using interconnect inductances to enhance injection
efficiency. This results in an excellent input sensitivity and a
wide locking range. Fabricated in a 65nm bulk CMOS
technology, the divider operates from 30.3 to 44 GHz (37%
locking range) while consuming 9mW from a 1.2V supply. The
measured phase noise is -131 dBc/Hz at 1-MHz offset whereas
the phase error between I-Q outputs is less than 1.44°.
Index Terms — Injection locked frequency divider, Direct
injection, Frequency synthesizer, 60 GHz sliding-IF
I. INTRODUCTION
The availability of high f
T
silicon IC technologies capable
of operating at millimeter wave (mm-wave) frequencies and
the extraordinary interest for high data rate (>1Gbps)
applications has motivated research and development of 60
GHz transceivers in recent years. The 7 GHz of contiguous
bandwidth available at 60 GHz, though very useful, poses
circuit design challenges especially for components like
VCOs, prescalers and PLLs in a direct conversion transceiver.
Therefore, alternative synthesizer friendly architectures based
on double-heterodyne, sliding-IF, low-IF and half-RF
architectures are being investigated.
Conventionally, prescalers in frequency synthesizers were
flip-flop based CML circuits [1]-[2]. However, these are
difficult to design reliably for 60 GHz owing to large RC time
constants of the devices which limit high frequency
performance. On the other hand, injection locked frequency
dividers can operate at very high frequencies but are
inherently narrowband due to their LC-tanks. Fig.1 shows the
system architecture of a sliding-IF 60 GHz transceiver. In this
system, the RF signal is converted to baseband in two steps.
The first mixing operation with the VCO transfers the RF
signal from 60 GHz to 20 GHz. The second mixing using
quadrature outputs from the prescaler down-converts the 20
Figure 1. Quadrature ILFD usage in a sliding-IF 60 GHz receiver
GHz signal to baseband. This approach relaxes the synthesizer
specifications and also avoids VCO pulling which is an issue
for direct conversion architectures. In this paper, feasibility of
ILFDs for 60 GHz sliding-IF transceivers is investigated by
implementing a 40 GHz divide-by-2 quadrature ILFD. In
addition, techniques to enhance locking range of the divider
are proposed which yield good measured results.
Section II describes the circuit design of the ILFD,
followed by a brief discussion, in section III, about layout and
technology used. Section IV includes the measurement results
and comparison with earlier published results and conclusions
are drawn in section V.
II. T
HEORY AND CIRCUIT DESIGN
In conventional ILFD’s the RF input signal is injected at
the common-source node of the oscillator which is inherently
running at double the fundamental frequency. However, the
transistor parasitic capacitances at this node “eat-up
significant part of the high frequency injection signal. To
counter this issue, shunt-peaking techniques have been
utilized, albeit at the cost of extra chip area [3]. In contrast, the
input signal, in this design, is directly injected across the tank
which improves injection efficiency considerably, thus
improving the locking range of the divider.
Majority of the published high frequency (above 30 GHz)
ILFDs, either based on conventional [3] or direct-injection [4]
978-1-4244-5458-7/10/$26.00 © 2010 IEEE SiRF 201057

Figure 2. Operation princple for quadrature operation of an ILFD
topologies provide differential outputs only. Therefore, the
need of quadrature outputs, especially for the system in Fig. 1,
is naturally felt. One option is to employ a passive poly-phase
filter after the ILFD to generate the quadrature outputs. This
approach has two main drawbacks. Firstly, a power hungry
buffer would be needed between the ILFD and filter to avoid
loading affects and this would result in phase noise
degradation. Secondly, variations in the RC values (in order of
15-25%) of the filter would require many tuning stages to
achieve acceptable quadrature accuracy. An alternative to the
poly-phase filter approach, used in this work, can be
understood by Fig. 2 (square pulses are used for simplicity). It
can be noted that a phase change of 180° at a frequency f
inj
corresponds to a phase change of 90° at f
inj
/2, as the signal
width is double at the latter frequency. Therefore, using this
concept at circuit level, the quadrature outputs can be obtained
by injecting the differential (180° spaced) VCO outputs (or
external injection signal) to two identical direct-injection
ILFD stages. The differential injection achieved by using V
inj
+
for one ILFD core and V
inj
-
for the second one also ensures
perfect loading symmetry for the VCO outputs.
The concern which still remains is the accuracy of the I-Q
outputs. Although, both ILFD stages can be designed and laid-
out identically, still the relative PVT variations for one stage
(or active/passive components) could be different from the
other resulting in I-Q mismatch. To address this issue, the two
ILFD stages are coupled to each other to force them to run in
quadrature as shown in Fig. 3. The coupling, called parallel or
anti-phase coupling, is achieved by connecting one ILFD
output to the other ILFD with transistors M7-M10 in parallel
to the cross coupled transistors M1, M2 and M4, M5. To
understand the forced quadrature operation of this setup, it can
be noted that each ILFD stage can be modeled as a gain stage.
Also, for any oscillator structure with feedback, the loop phase
must be 0° or 360°. Since the crossed connection (due to anti-
phase coupling) between the ILFD’s represent a phase shift of
180°, the two stages must have an additional phase shift of
180°. Hence, the phase shift across one stage is 90° ensuring
quadrature operation.
Figure 3. 40 GHz Q-ILFD circuit schematic
The Q-ILFD design is based on two identical free running
oscillators, each formed by two NMOS transistors (M1-M2 &
M5-M6) cross-coupled together to compensate the loss of the
resonator. The inductors of the two ILFD stages are single
turn, top-metal symmetric octagonal structures. The width of
the metal trace is 9µm with an inner radius of 63µm. The
guard-ring around the inductor is placed 10µm away from the
signal trace and area of the inductor is 209x188 µm
2
. The
resulting inductance at 20 GHz is 310pH with a Q-factor of
~25. The varactors are accumulation MOS (AMOS) type and
two of them are connected back-to-back to provide a
common-mode node for tuning. To decrease the series
resistance, the varactors are chosen to have multiple fingers.
The width and length per finger is 2.1µm and 300nm
respectively with 14 fingers in total. The resulting capacitance
and Q-factor for a tuning voltage of 0 — 1.2V is 128 — 34fF
and 5—18, respectively.
The dimensions of transistors M7-M10 determine the
coupling strength between the two stages. If they are chosen
too large, considerable parasitic capacitance is added to the
tank. On the contrary, if they are chosen too small the
coupling between the stages is weak and quadrature accuracy
is degraded. Therefore, an optimized width of 7.5µm is chosen
which is one-fourth of the cross-coupled transistors M1-M4
(30µm). The injection transistors M3 and M6 are 9µm wide
with minimum channel length. The 150 poly-silicon based
resistors in the tail node provide common-mode rejection and
define the DC current through the ILFD. Differential
common-source output buffers are employed for measurement
purpose and matched to 50 environment.
The use of inductors makes it unavoidable to use long
interconnects from the bond-pads to the injection transistors.
As shown in Fig. 5, transmission lines are used where space is
available, however, close to the core, the interconnect has to
be an un-avoidable metal strip which in this case is ~78µm
long. Due to capacitive input of the injection transistors, there
is an inherent power mismatch between the gate input and the
signal generator equipment. Consequently, at high
frequencies, part of the injection signal is lost in the parasitic
capacitance. A useful solution adopted in this work, is to
utilize the required interconnect for power matching at the
input of injection transistor. The interconnect is implemented
as a micro-strip transmission line and shielded in a cavity-like
structure (for isolation). Cadence parametric simulations are
58

114
115
116
117
118
119
120
121
122
30 33 36 39 42 45
Inductance (pH)
Frequency (GHz)
Me1 Me2 Me3
Me4 Me5 Me6
Figure 4. Inductance of a 2.5µm wide, 78µm long interconnect in different
metal layers
used to determine the required inductance for maximum
power matching. After optimization, EM simulations are done
in ADS Momentum to determine the inductance per unit
length for different metals in the technology stack as shown in
Fig. 4. The metal layer Me3, which is closest to the required
value is used for the interconnect layout. Due to this injection
enhancement technique, input sensitivity is improved and for
the same output power, the required input signal power is
almost halved. This is proved by the measured low sensitivity
discussed in section IV.
III. L
AYOUT AND TECHNOLOGY
The layout of the divider is done carefully and compactly to
reduce unnecessary parasitics. The RF signal paths between
the tank and negative gm-cells are kept short and narrow lines
are avoided to reduce resistive losses. The coupling transistors
(M7-M10) are perfectly matched to ensure identical
oscillation frequencies for both stages. In addition, ground
meshing is used under the RF paths and decoupling capacitors
are included for the voltage supplies. The differential input
and outputs use 50 transmission lines (TLs) to the bond-
pads. These TLs are coplanar waveguide based with lateral
ground plane consisting of all metal layers “sandwiched”
together using large number of vias, thus providing excellent
noise isolation. The width of the signal path of the TL is 5µm
and spacing from the ground plane is 4.22µm.
The dividers are fabricated in TSMC bulk CMOS 65nm
LP (low-power) process having six metallization layers. The
process offers MIM capacitors and poly-silicon resistors. The
measured f
T
of NMOS and PMOS transistors is 140 GHz and
80 GHz, respectively. As shown in Fig. 5, the area of the
divider is bond-pad limited and occupies 900x750µm
2
in
which the complete core is located between the two coils and
occupies 80x100 µm
2
.
IV. M
EASUREMENT RESULTS
The 40 GHz ILFD was measured on-wafer. The input 40
GHz signal from an Agilent signal generator is applied to a
single-to-differential converter (180° hybrid) and then passed
on the RF probe. The output differential signal is converted to
Figure 5. Die Micrograph of the 40 GHz Q-ILFD
single-ended using a similar hybrid and observed by an
Agilent spectrum analyzer (E4446A). The phase noise is also
measured by the spectrum analyzer.
The free-running frequency of the ILFD is first measured
by switching “off” the injection signal. It starts oscillating at
1V supply whereas the maximum tuning range from 17 to
20.5 GHz is obtained with a 1.2 V supply. After fixing the
tuning voltage of the varactor to a certain value, the injection
signal is then switched “on” close to double the self-oscillating
frequency for that particular V
tune
. The input power is reduced
to determine the minimum value for which the ILFD still
locks to the input signal. Similarly, input sensitivity for
different varactor tuning voltage is measured, three of which
are plotted in Fig. 6. The ILFD can operate from 30.3GHz to
44 GHz (14 GHz or 37% locking range). The locking range
for one tuning voltage is about 6 GHz, thus only three V
tune
values are required to cover the complete operating range. The
improved injection efficiency due to direct injection topology
and input power matching technique, results in the required
input power close to free-running frequency of the ILFD to be
as low as -38 dBm. The simulated sensitivity curves are also
plotted for reference and match closely to the measured
curves. The low voltage operation of the ILFD is also verified
by reducing the supply voltage. The divider can operate with a
reduced supply of 1V resulting in a locking range of 8 GHz.
The phase noise of the ILFD is -131.6 dBc/Hz at 1-MHz
from a 18.95 GHz output frequency (Fig. 7). The phase noise
of the signal generator at double the frequency is -125 dBc/Hz
which is close to the theoretical 6 dB difference due to
frequency division. The phase noise variation over the
complete operating range is +
2.5 dB. The combined power
consumption of the I-Q dividers is 9mW from a 1.2V supply.
The output buffers used for measurement purpose consume
12mW. The locked spectrums at minimum and maximum
operating frequencies are shown in Fig. 8. Due to usage of
considerable number of cables (six in total), hybrids and
needed connecters, considerable power loss is observed in the
measured spectrum. However, after de-embedding these losses
the output power of the ILFD is between -4 and -8 dBm. The
I-Q phase error could not be measured reliably due to the
absence of a stable trigger signal during oscilloscope
measurements; however, post-layout simulations based on RC
59

-60
-50
-40
-30
-20
-10
0
30 32 34 36 38 40 42 44 46
Min. Input Power (dBm)
Frequency (GHz)
Vtune=1.2 Vtune=0 Vtune=0.6
Vtune=0_Sim Vtune=0.6_Sim Vtune=1.2_Sim
-7
-14
-21
-28
-35
-42
Figure 6. Input sensitivity curves of 40 GHz Q-ILFD
extraction demonstrate a phase error less than 1.44° over the
complete locking range.
Table I shows a comparison of the presented frequency
divider with published results. As frequency dividers with
identical operating frequencies could not be found, the divide-
by-2 Q-ILFD of this work is compared with ILFDs operating
at higher and lower frequencies. It offers the second-highest
locking range with lowest power of -2 dBm required at the
locking range corners. Due to the input matching technique,
the input power of -38 dBm is lower than the designs in [4-
5][7]. As the only quadrature divider in the table, the power
consumption is comparable to non-quadrature designs in [4]-
[5]. The measured phase noise is also lower than all cited
works in Table I.
Figure 7. Phase noise for a 18.95 GHz divided output
V. CONCLUSIONS
We have presented a mm-wave quadrature injection locked
frequency divider as an enabling component for a 60 GHz
sliding-IF systems. The measured locking range of the ILFD is
14 GHz (37 %) while consuming 9 mW from a 1.2 V supply.
The phase noise for a 18.95 GHz divided output is -131
dBc/Hz at 1 MHz offset. The minimum input injection power
required is as low as -38 dBm. The low input sensitivity is
achieved by employing direct injection and input power
matching. The latter technique utilizes interconnect inductance
to cancel the parasitic capacitance of the input injection
transistor, thus no area or performance penalty is introduced.
Figure 8. Output spectrum for (a) Min. input frequency (30.3 GHz) (a)
Max. input frequency (44 GHz)
TABLE I. C
OMPARISON WITH PUBLISHED RESULTS
[4] 180 43 - 49 13 0 8 -120
[5] 130 50 - 62 21.42 0 10.8 -124.9
[6] 130 25 - 31.2 22 0 1.86 -130
[7] 90 35.7 - 54.9 42.3 5 0.8 -118.4
This work 65 30.3 - 44 36.9 -2 9* -131.6
Ref
Process
(nm)
Op. Freq
(GHz)
Pin
(dBm)
Power
(mW)
Ph. Noise
(dBc/Hz @ 1 MHz)
L. R.
(%)
* Total consumption including both I- Q divider
ACKNOWLEDGMENT
The authors would like to thank Philips Research
Eindhoven for technology access.
R
EFERENCES
[1] H. M. Cheema, R. Mahmoudi, M. A. T. Sanduleanu, and A. van
Roermund, "A Ka Band, Static, MCML Frequency Divider, in Standard
90nm-CMOS LP for 60 GHz Applications," IEEE Radio Frequency
Integrated Circuit Symposium (RFIC), pp. 541-544, June 2008.
[2] Y. Mo, E. Skafidas, R. Evans, and I. Mareels, "50 GHz static frequency
divider in 130 nm CMOS," Electronics Letters, vol. 44, no. 4, pp. 285-
286, 2008.
[3] H. Wu, A. Hajimiri, “A 19GHz 0.5mW 0.35μm CMOS Frequency
Divider with Shunt-Peaking Locking-Range Enhancement,” ISSCC
Dig. Tech. Papers, pp. 412-413, Feb., 2001.
[4] Yi-Jan Emery et.al.,“A Wide Operation Range CMOS Frequency
Divider for 60 GHz Dual-Conversion Receiver,” IEEE Radio
Frequency Integrated Circuit Symposium (RFIC), June 2006.
[5] Yu-Hang Wong, Wei-Heng Lin, Jeng-Han Tsai, Tian-Wei Huang, “A
50-to-62GHz Wide-Locking-Range CMOS Injection-Locked
Frequency Divider with Transformer Feedback,” IEEE Radio
Frequency Integrated Circuit Symposium (RFIC), pp. 435-438, June
2008.
[6] Hsien-Ku Chen, Da-Chiang Chang, Ying-Zhong Juang, Shey-Shi Lu,
“A 30-GHz Wideband Low-Power CMOS Injection-Locked Frequency
Divider for 60-GHz Wireless-LAN,” IEEE Microwave and Wireless
Components Letters, pp. 145-147, Feb. 2008.
[7] Tang -Nian Luo, Yi-Jan Emery et.al.,“A 0.8-mW 55-GHZ Dual-
Injection-Locked CMOS Frequency Divider,” IEEE Transactions on
Microwave Theory and Techniques, vol. 56, no. 3, pp. 620-625, March
2008.
60
Citations
More filters

Journal ArticleDOI
TL;DR: This solution compares favorably with the state of the art and shows the largest fractional bandwidth (44%) among the quadrature generators at frequencies greater than 20 GHz, to authors’ knowledge.
Abstract: Precise generation of quadrature signals over a wide frequency range is a key function for the next-generation 5G communication systems. In this paper, we present a wideband quadrature generator based on a single-stage polyphase filter (PPF). A phase detector senses the phase error from quadrature signals generated by a single-stage PPF, and a feedback circuit continuously tunes the filter center frequency to the input signal frequency by varying the polyphase resistance of an nMOS device in triode. Transformer-based resonant circuits at the input and output of the PPF ensure wide bandwidth and low loss. Prototypes have been realized in a 55-nm CMOS technology. Tailored to the next-generation 5G systems for cross-network interoperability requirements, the measured quadrature generator shows an image rejection ratio IRR > 40 dB over a bandwidth from 28 to 44 GHz. The power consumption is 36 mW for the PPF and buffers, and 3 mW only for the calibration loop. One key aspect of the proposed solution is its robustness over process, voltage and temperature (PVT), one of the weak aspects of alternatives proposed in the literature. This solution compares favorably with the state of the art and shows the largest fractional bandwidth (44%) among the quadrature generators at frequencies greater than 20 GHz, to authors’ knowledge.

7 citations


Cites background from "A 30 to 44 GHz divide-by-2, quadrat..."

  • ..., 56–78 GHz) in combination with a divide-by-2 circuit would naturally yield quadrature signals at output [26]....

    [...]


DOI
01 Jan 2010
TL;DR: In this work, frequency synthesizers as enabling sub-systems for 60 GHz transceivers have been presented and a systematic top-down approach was adopted which included the system analysis followed by design and implementation of critical synthesizer components and finally their combined integration to form the proposed synthesizer.
Abstract: The 60 GHz license-free frequency band offers the possibility of multi-gigabit per second wireless transmission satisfying the increasing demand of data intensive applications over short distances. Over the last decade, aggressive down-scaling of CMOS technologies coupled with an intensive research effort has made the realization of complete 60 GHz systems, a reality. In this work, frequency synthesizers as enabling sub-systems for 60 GHz transceivers have been presented. In order to accomplish an accurately functioning overall system, a systematic top-down approach was adopted which included the system analysis followed by design and implementation of critical synthesizer components and finally their combined integration to form the proposed synthesizer. Experience of the complete design flow at mm-wave frequencies was attained that, apart from circuit design solutions, included specialized layout and measurement techniques. Chapter 2 laid down the system architecture of the synthesizer. The channelization specifications for the synthesizer were extracted from the IEEE 802.15.3c which is a standard still in works. The proposed channels were either based on 2 GHz HRP for data intensive applications or 1 GHz and 500 MHz LRP channels for moderate and low data rate applications, respectively. A flexible synthesizer architecture was proposed with the aim to support a number of potential frequency conversion techniques which can be adopted for a 60 GHz transceiver. While re-using the same back-end and by adopting flexible synthesizer front-ends, the proposed architecture supported the sliding-IF topology and the direct conversion topology with and without a frequency tripler. An overview of synthesizer basics was also included followed by calculations and system level simulations of the overall system. In chapter 3, the impact of layout parasitics and sensitivity of measurements at mm-wave frequencies and the techniques employed in this work to address them were elaborated. For mm-wave layout there are no-rules but only guidelines. Distributed analysis at mm-wave frequencies is not only required due to small wavelengths but also because the interconnect parasitics become of the same order as the passive structures. Therefore, a maximum tolerable interconnect length based on the operation frequency and the circuit application needs to be determined. Furthermore, the circuit floor-planning becomes important and should be done in a way to minimize interconnect lengths. In addition to the usual RC-extraction, EM-solvers need to be utilized for critical interconnects for inductance extraction. In order to reduce substrate losses, cross-talk and coupling between components, shielding techniques such as meshed grounding, coplanar transmission lines, and guard-rings should be utilized. The second half of chapter 3 was dedicated to mm-wave IC measurement issues such as losses, mismatches and variation in the equipment, cables, connectors, probe position and temperature. In general, the measurement plane has to be shifted close to the DUT by performing accurate and regular calibrations. Furthermore, the measurement environment should be kept quiet to avoid external noise corrupting the on-chip signals. To obtain stable and repeatable results, physical change in the setups must be avoided and a considerable number of samples should be measured to average out the unwanted contributions in the measured results. Chapter 4 focused on the synthesizer front-end components which operate at the highest frequencies in the synthesizer and are the most challenging blocks. A step wise approach was adopted, starting with individual component design of the prescalers and VCOs and concluding with an integrated front-end. An overview of different prescaler architectures revealed that static and dynamic frequency dividers are easy to design and provide wide locking range; however, they fall short of reaching close to 60 GHz. Injection locked frequency dividers, on the other hand, are able to operate at mm-wave frequencies but their narrow-band nature results in smaller locking range. Thus, circuit design techniques have been adopted to improve the latter characteristic. Three examples of injection locked frequency dividers were presented. The 40 GHz divide-by-2 quadrature ILFD based on direct injection used an input power matching technique by utilizing interconnect inductance to cancel-out parasitic capacitance of the injection transistor. This enhanced the injection efficiency and resulted in a wide locking range. The 60 GHz divide-by-3 ILFD on the other hand addressed the locking range issue by adopting harmonic enhancement through resistive feedback. The last prescaler presented for the proposed synthesizer combined the divide-by-2 and divide-by-3 operations in one circuit, thus simplifying the overall system architecture considerably. New figure-of-merits were introduced for frequency dividers for a proper comparison especially between ILFDs with or without varactor tuning. The introduced FOMs also incorporated the DC power consumption and input sensitivity, which are important performance benchmarks for ILFDs. The second major section of chapter 4 was dedicated to the voltage controlled oscillator. An overview of various VCO architectures was presented among which LC based VCOs were found to be suitable for 60 GHz frequency operation with reasonable tuning range and phase noise. Three LC-VCO circuits were presented next. The VCO for the 40 GHz front-end was a complementary cross-coupled structure and employed differential tuning for the capacitive tuning circuit. Two I-Q VCOs for the 60 GHz synthesizer front-end were presented next. The first was based on active coupling using transistors whereas the second was based on passive coupling using on-chip transformers. The transformer was measured as a separate test-structure and provided reasonable between EM simulations and measurements. By way of analysis, it was found that a dual-band VCO (operating at 40 and 60 GHz) utilizing switches and with satisfactory FTR was very difficult to achieve. This was because either the losses of the switch were too high, which degraded the tank Q-factor, or the fixed capacitance added to the tank was too large, which decreased the tuning range. Therefore, two separate VCOs operating at the aforementioned frequencies were adopted as a way-forward for synthesizer front-end integration. The last section of chapter 4 presented the integrated synthesizer front-ends at 40 and 60 GHz which was an important step towards complete system integration. The main challenge in combining the two front-end components was to align their operating ranges. In chapter 5, the synthesizer back-end components including the low frequency dividers, phase frequency detector, charge pump and loop filter were presented. Although working at lower frequencies, these components entailed challenges such as accuracy, matching and robustness. Two approaches for feedback division namely cascaded divide-by-2 stages and mixer based division were demonstrated. The former was optimized for low power consumption by reducing the transistor dimensions and moderately increasing the load resistors. The mixer based approach offered further reduction of power consumption; however, it required a fixed and accurate LO for down-converting the ILFD output to a frequency close to the reference frequency of the synthesizer. The PFD, based on D-flip-flops, was constructed by custom made NAND gates and the dead-zone was eliminated by inserting intentional delay in the reset path. The charge-pump was optimized for matching between up and down currents and voltage drops across transistors were equalized by using dummy transistors. The second order loop filter was combined with the PFD and charge-pump to determine the response of the back-end to increasing or decreasing phase and frequency difference. Finally in chapter 6, building on the components and sub-circuit designs of preceding chapters, complete synthesizers based on our proposed flexible architecture were presented. Using the expertise from chapter 4 of VCO, ILFD and front-end design, the integration of the complete 40 GHz synthesizer was considerably simplified and the measured and simulated results matched very closely. Based on the 40 GHz components, a single-mode synthesizer for 60 GHz sliding-IF system was presented first. It demonstrated sufficient locking range to cover the 60 GHz frequency band from 57 to 65 GHz. Furthermore, the measured phase noise, settling time and power consumption were comparable to the state-of-the-art published synthesizers. The next synthesizer replaced the divider chain in the feedback loop with a mixer operated by an external LO signal. For testing purposes, the reference frequency was fixed and the output of the synthesizer was set by varying the mixer LO frequency. At simulation level, this setup offered savings in silicon area and power consumption. However, it had a drawback of an extra LO frequency. Finally, a dual-mode synthesizer matching the proposed architecture was presented which included the 40 and 60 GHz VCOs, both connected to a single dual-mode ILFD. In the 60 GHz direct-conversion mode, the tuning-range of the VCO was found to be a limiting factor and the presented design could only cover eleven out of twelve 500 MHz LRP channels. Combining the performance parameters of the two individual synthesizers, the dual-mode synthesizer provides an elegant solution for sliding-IF as well as direct-conversion transceivers with or without using a frequency tripler.

4 citations


Journal ArticleDOI
Abstract: This paper presents a 144 GHz divide-by-2 injection locked frequency divider (ILFD) with inductive feedback developed in a commercial 90-nm Si RFCMOS technology. It was demonstrated that division-by-2 operation is achieved with input power down to -12 dBm, with measured locking range of 0.96 GHz (144.18 - 145.14 GHz) at input power of -3 dBm. To the authors' best knowledge, this is the highest operation frequency for ILFD based on a 90- nm CMOS technology. From supply voltage of 1.8 V, the circuit draws 5.7 mA including both core and buffer. The fabricated chip occupies 0.54 mm × 0.69 mm including the DC and RF pads.

3 citations


Journal ArticleDOI
Abstract: This paper proposes a direct injection-locked frequency divider (ILFD) with a wide locking range in the Ka-band. A complementary cross-coupled architecture is used to enhance the overdriving voltage of the switch transistor so that the divider locking range is extended efficiently. New insights into the locking range and output power are proposed. A new method to analyze and optimize the injection sensitivity is presented and a layout technique to reduce the parasitics of the cross-coupled transistors is applied to decrease the frequency shift and the locking range degradation. The circuit is designed in a standard 90-nm CMOS process. The total locking range of the ILFD is 43.8% at 34.5 GHz with an incident power of −3.5 dBm. The divider IC consumes 3.6 mW of power at the supply voltage of 1.2 V The chip area including the pads is 0.5 × 0.5 mm2.

2 citations


Additional excerpts

  • ...[9] 65-nm CMOS 2 30....

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Proceedings ArticleDOI
01 Dec 2010
TL;DR: This paper presents a low power sub-harmonic up-convert mixer for 60 GHz unlicensed-band applications and is fabricated using Jazz's SiGe 0.18 µm high frequency process, able to achieve a spurious rejection better than 20 dBc with reference to RF frequency.
Abstract: This paper presents a low power sub-harmonic up-convert mixer for 60 GHz unlicensed-band applications and is fabricated using Jazz's SiGe 0.18 µm high frequency process. The mixer operates with a RF bandwidth of 9 GHz centered at 60 GHz, a LO at 24 GHz and has a wideband of 3.5 GHz around an IF frequency of 12 GHz. It is able to achieve −0.1 dB of conversion gain with a differential common emitter buffer. The mixer is able to meet the high linearity specifications with an input referred P1dB of −12.3 dBm while achieving extremely low LO drive requirements of −14 dBm. The up-conversion mixer is able to achieve a spurious rejection better than 20 dBc with reference to RF frequency. It occupies a silicon area of 880 um × 780 um including both RF and DC probe pads. Mixer core dissipates only 1.7 mA of current from a 1.8 V voltage supply.

1 citations


Cites methods from "A 30 to 44 GHz divide-by-2, quadrat..."

  • ...sliding-IF system architecture [11], a two step conversion approach is adopted....

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References
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Proceedings ArticleDOI
05 Feb 2001
Abstract: A frequency divider is an essential building block and one of the major sources of power dissipation in widely-used frequency synthesizers. As the output frequency of the synthesizer increases, the trade-off between the speed and power dissipation of dividers becomes more critical. Narrow-band injection-locked frequency dividers (ILFD) dissipate a fraction of the energy stored in the tank, which is determined by the quality factor, Q, of the resonator, in every cycle. Therefore, they have fundamentally lower power dissipation than wide-band dividers. Due to their narrow-band nature, ILFDs work in a limited frequency range (locking range). In this paper, shunt-peaking is used as an approach to increase the locking range and lower the power dissipation at higher frequencies.

142 citations


"A 30 to 44 GHz divide-by-2, quadrat..." refers background in this paper

  • ...Majority of the published high frequency (above 30 GHz) ILFDs, either based on conventional [3] or direct-injection [4]...

    [...]

  • ...To counter this issue, shunt-peaking techniques have been utilized, albeit at the cost of extra chip area [3]....

    [...]



Journal ArticleDOI
Abstract: This paper presents the dual-injection-locking technique to enhance the locking range of resonator-based frequency dividers. By fully utilizing the voltage and current injection of the input signal, the divider locking range is extended significantly. The 0.8-mW dual-injection-locked frequency divider was developed in 90-nm digital CMOS technology. The total chip size is 0.77 mm times 0.5 mm. Without any varactor or inductor tuning, the input signal frequency coverage of the divider is from 35.7 to 54.9 GHz. Combined with the excellent locking range and sub-milliwatt power consumption, the figure-of-merit of this work surpasses those of the previous resonator-based dividers by more than one order.

103 citations


"A 30 to 44 GHz divide-by-2, quadrat..." refers methods in this paper

  • ...Due to the input matching technique, the input power of -38 dBm is lower than the designs in [45][7]....

    [...]


Proceedings ArticleDOI
15 Jul 2008
Abstract: A 50-to-62 GHz injection-locked frequency divider (ILFD) with transformer feedback technique is designed in 0.13-mum CMOS technology for wide locking range. The measurement results show that the free-running frequency is 55.3 GHz and the total locking range is 12 GHz (>20%) at the input power level of 0 dBm while consuming 10.8 mW from a 0.9 V power supply. The phase noise of the divider is -124.93 dBc/Hz at 1 MHz offset from the carrier. This wide locking range ILFD is suitable for integration into a phase-lock-loop (PLL) system because of its small size and no need of extra control signal.

29 citations


"A 30 to 44 GHz divide-by-2, quadrat..." refers methods in this paper

  • ...As the only quadrature divider in the table, the power consumption is comparable to non-quadrature designs in [4][5]....

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Journal ArticleDOI
Abstract: A 30-GHz wide locking-range (25%) injection-locked frequency divider (ILFD) with small power consumption (1.86 mW) is presented. The locking range of the ILFD is extended by reducing the quality factor of resonant tank. Besides, the output power level of second harmonic is lower than that of fundamental component by 37 dBc due to the new output buffer where the second harmonic can be cancelled. The proposed wideband ILFD is implemented in 0.13-mum standard CMOS process. It achieves a wide locking-range of 6.2 GHz (25 %) without any frequency tuning mechanism under the small power consumption of 1.86 mW and the highest figure-of-merit of 12.4 (%/mW) among all reported state-of-the-art CMOS ILFD.

26 citations


Frequently Asked Questions (1)
Q1. What are the contributions in "A 30 to 44 ghz divide-by-2, quadrature, direct injection locked frequency divider for sliding-if 60 ghz transceivers" ?

This paper presents a wideband 40 GHz divide-by-2 quadrature injection locked frequency divider ( Q-ILFD ) as an enabling component for sliding-IF 60 GHz transceivers.