A 32 BIT MAC unit design using Vedic multiplier and reversible logic gate
19 Mar 2015-pp 1-6
TL;DR: The Vedic Multiplier and the Reversible Logic Gates has Designed and implemented in the multiply and Accumulate Unit (MAC) and that is shown in this paper.
Abstract: The Vedic Multiplier and the Reversible Logic Gates has Designed and implemented in the multiply and Accumulate Unit (MAC) and that is shown in this paper A Vedic multiplier is designed by using Urdhava Triyagbhayam sutra and the adder design is done by using reversible logic gate Reversible logics are also the fundamental requirement for the emerging field of Quantum computing The Vedic multiplier is used for the multiplication unit so as to reduce partial products and to get high performance and lesser area The reversible logic is used to get less power The MAC is designed in Verilog HDL and the simulation is done in Modelsim, Xilinx 142 and synthesis is done in both RTL compiler using cadence as well as Xilinx The chip design for the proposed MAC is also carried out
Citations
More filters
01 Aug 2017
TL;DR: The proposed multiplier Sampoornam is used for designing a 4-bit Multiplier accumulator unit (MAC) unit and is extended up to 64-bit using Vedic scaling technique and is comparatively time efficient than the present day multipliers such as (a∗b) algorithm, Booth and Wallace.
Abstract: Multipliers are core components of most of the digital signal processing algorithms which lie in critical delay path and decide performance of any algorithm. Over the years various approaches have been proposed to reduce the computational overhead of conventional multipliers. Vedic mathematics has been one among them. In this paper, a novel multiplier unit is proposed which integrates the advantage of each of the sutras. “Sampoornam” alias “Absolute vedic” multiplier is designed to have a specialized logic unit that decides which multiplier is to be used for optimum results based on the types of input, improving efficiency. The proposed multiplier Sampoornam is used for designing a 4-bit Multiplier accumulator unit (MAC) unit and is extended up to 64-bit using Vedic scaling technique. Sampoornam is comparatively time efficient than the present day multipliers such as (a∗b) algorithm, Booth and Wallace. The 4-bit MAC unit developed using sampoornam has 25 % reduction in time delay compared to MAC developed using Wallace multiplier. Similar trend is observed as the number of bits is increased.
15 citations
Cites methods from "A 32 BIT MAC unit design using Vedi..."
...In recent times 32bit MAC unit using Vedic maths technique is reported [3]....
[...]
TL;DR: A high-speed 16 × 16 Vedic multiplier was designed using Urdhva Tiryagbhyam (UT) sutra, which is derived from Vedic mathematics, and a new method based on Elliptic Curve Cryptography (ECC) system for encryption and decryption using Vedic multiplication is proposed.
Abstract: Multipliers act as processors and take on the notable work of many computing frameworks. The speed of the processor is profoundly affected by the speed of their multipliers. In order to improve the system speed, faster and more efficient multipliers should be used. A Vedic multiplier is one of the best solution that can be used to perform multiplications at a faster rate by eliminating the steps that are not needed in usual multiplication process. Power consumption is another critical issue in embedded systems that cannot be ignored. Reversible logic has become notable in the recent years because of its potential to reduce power utilization, which is a major concern in digital design. In this work, a high-speed 16 × 16 Vedic multiplier was designed using Urdhva Tiryagbhyam (UT) sutra, which is derived from Vedic mathematics. This is a simple structure as well as an unbeatable combination for creating any complex multiplication operations for services where speed is of prime importance. This work also proposes a new method based on Elliptic Curve Cryptography (ECC) system for encryption and decryption using Vedic multiplication. By using Vedic Multiplication in ECC the processing time is perfectly reduced. The proposed Elliptic curve cryptography method is much faster than other elliptic curve cryptographic algorithms. Compared to other cryptographic techniques, the key size required to provide equivalent security is small in ECC.
10 citations
01 Jan 2019
TL;DR: It has been proved that the proposed DKG gate with Vedic multiplier-adder is having the high speed of operation.
Abstract: The design of Multiplier-Accumulator (MAC) unit can be implemented by using the Vedic multiplier along with the reversible logic gates. The designing of Vedic multiplier is designed by using the new sutra called “Urdhava Triyagbhayam”. The performance of the MAC operation depends on the multiplier unit and the adder units. Here the designing of a multiplier and an adder can be designed by using the reversible gates to get the high speed of operation and also a Vedic multiplier is used for the higher performance, lesser area and to reduce the partial products. Nowadays reversible computing will take a more preferable for low power dissipation, higher speed of operation. Here, we proposed an 8, 16, 32, 64-bit Vedic multiplier is designed by using the carry save adder(CSA), the kogge stone adder(KSA) and the DKG adder out of these the proposed DKG gate adder is having the high speed of operation. The comparative analysis is carried out among the ripple carry adder (RCA), carry save adder, kogge stone adder. Finally, it has been proved that the proposed DKG gate with Vedic multiplier-adder is having the high speed of operation. The overall Simulation and synthesis process is carried out with Xilinx ISE 14.7 and is dumped on the FPGA Zynq board.
8 citations
10 Jul 2018
TL;DR: This paper has focused on proposing the MAC architecture using an integrated Hybrid binary Multiplier and integrated CLA adder network which is a combination of Karatsuba algorithm and Urdhva Triyagbhyam sutra from vedic mathematics.
Abstract: Wherever there is a need for high-performance computing applications there is an evident demand of an efficient high-speed multiplier. Multiplication takes most significant time as compared to other arithmetic operations. Multipliers are the most essential blocks in every high-performance computing architecture like Digital signal processing (DSP). MAC unit which consist of Multiplier and Accumulator plays an important role to decide the performance of any DSP block. The better performance of MAC unit fulfills the parameter of fast computation and real-time processing capabilities of a DSP. Over the years number of ideas have been proposed to improve the performance and mitigate the excessive partial product term generation during conventional multiplication approach. In this paper, we have focused on proposing the MAC architecture using an integrated Hybrid binary Multiplier and integrated CLA adder network. The integrated multiplier is a combination of Karatsuba algorithm and Urdhva Triyagbhyam sutra from vedic mathematics. CLA adder network consist of CLA and conditional sum adder which helps to reduce addition time by performing parallel addition. Mentioned design is implemented in Verilog HDL using Libero SOC PolarFire v2.1 tool, targeting its PolarFire FPGA family and MPF300T_ES-IFCG484E device.
6 citations
06 Mar 2020
TL;DR: Vedic Multiplier is one of the efficient multipliers to decrease the delay and improve the performance and introduces Reversible logic gates which dissipate less power compared to Conventional logic.
Abstract: Multiplier and Adder are the primary components to design a MAC unit. It has two stage of operations; one is to find the product of two numbers and other is adding the product to the other number and stores it in the accumulator. Power, Delay and LUT utilization are the important parameters to decide the performance of a processors. Introducing Reversible logic gates which dissipate less power compared to Conventional logic. Vedic Multiplier is one of the efficient multipliers to decrease the delay and improve the performance. Also, various reversible adders are constructed to add the partial outputs. The proposed work shows the performance of different designs used in a MAC unit using reversible logic.
4 citations
References
More filters
IBM1
TL;DR: This result makes plausible the existence of thermodynamically reversible computers which could perform useful computations at useful speed while dissipating considerably less than kT of energy per logical step.
Abstract: The usual general-purpose computing automaton (e.g.. a Turing machine) is logically irreversible- its transition function lacks a single-valued inverse. Here it is shown that such machines may he made logically reversible at every step, while retainillg their simplicity and their ability to do general computations. This result is of great physical interest because it makes plausible the existence of thermodynamically reversible computers which could perform useful computations at useful speed while dissipating considerably less than kT of energy per logical step. In the first stage of its computation the logically reversible automaton parallels the corresponding irreversible automaton, except that it saves all intermediate results, there by avoiding the irreversible operation of erasure. The second stage consists of printing out the desired output. The third stage then reversibly disposes of all the undesired intermediate results by retracing the steps of the first stage in backward order (a process which is only possible because the first stage has been carried out reversibly), there by restoring the machine (except for the now-written output tape) to its original condition. The final machine configuration thus contains the desired output and a reconstructed copy of the input, but no other undesired data. The foregoing results are demonstrated explicitly using a type of three-tape Turing machine. The biosynthesis of messenger RNA is discussed as a physical example of reversible computation.
3,497 citations
"A 32 BIT MAC unit design using Vedi..." refers background in this paper
...Landauer [18] proved that the usage of traditional irreversible circuits leads to power dissipation and Bennet [17] showed that a circuit consisting of only reversible gates does not dissipate power....
[...]
...Fan-out is not permitted Loops or feedbacks are not permitted Garbage outputs must be Minimum Minimum delay Minimum quantum cost Zero energy dissipation [17]...
[...]
TL;DR: This paper proposes three new reversible logic gates; two of the proposed gates can be employed to design online testable reversible logic circuits and can be used to implement any Boolean logic function.
Abstract: Conventional digital circuits dissipate a significant amount of energy because bits of information are erased during the logic operations. Thus, if logic gates are designed such that the information bits are not destroyed, the power consumption can be reduced dramatically. The information bits are not lost in case of a reversible computation. This has led to the development of reversible gates. This paper proposes three new reversible logic gates; two of the proposed gates can be employed to design online testable reversible logic circuits. Furthermore, they can be used to implement any Boolean logic function. The application of the reversible gates in implementing several benchmark functions has been presented.
153 citations
TL;DR: It has been shown that the modified designs outperform the existing ones in terms of number of gates, number of garbage outputs, delay, and quantum cost.
134 citations
15 Jul 2009
TL;DR: The efficiency of Urdhva Triyagbhyam-Vedic method for multiplication is proved which strikes a difference in the actual process of multiplication itself, which enables parallel generation of intermediate products, eliminates unwanted multiplication steps with zeros and scaled to higher bit levels using Karatsuba algorithm.
Abstract: The ever increasing demand in enhancing the ability of processors to handle the complex and challenging processes has resulted in the integration of a number of processor cores into one chip. Still the load on the processor is not less in generic system. This load is reduced by supplementing the main processor with Co-Processors, which are designed to work upon specific type of functions like numeric computation, Signal Processing, Graphics etc. The speed of ALU depends greatly on the multiplier. In algorithmic and structural levels, numerous multiplication techniques have been developed to enhance the efficiency of the multiplier which concentrates in reducing the partial products and the methods of their addition but the principle behind multiplication remains the same in all cases. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. Employing these techniques in the computation algorithms of the coprocessor will reduce the complexity, execution time, area, power etc. Though there are many sutras employed to handle different sets of numeric, exploring each one gives new results. Our work has proved the efficiency of Urdhva Triyagbhyam-Vedic method for multiplication which strikes a difference in the actual process of multiplication itself. It enables parallel generation of intermediate products, eliminates unwanted multiplication steps with zeros and scaled to higher bit levels using Karatsuba algorithm with the compatibility to different data types. This sutra is to be used to build a high speed power efficient multiplier in the coprocessor.
123 citations
"A 32 BIT MAC unit design using Vedi..." refers background in this paper
..., The word “Vedic” is derived from the word “Veda” which means the power house of all knowledge and divine [2, 3]....
[...]
02 Jun 2011
TL;DR: A high speed complex multiplier design using Vedic mathematics is presented in this paper, where partial products and sums are generated in one step which reduces the carry propagation from LSB to MSB.
Abstract: Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique technique of calculations based on 16 Sutras (Formulae). A high speed complex multiplier design (ASIC) using Vedic Mathematics is presented in this paper. The idea for designing the multiplier and adder/sub-tractor unit is adopted from ancient Indian mathematics “Vedas”. On account of those formulas, the partial products and sums are generated in one step which reduces the carry propagation from LSB to MSB. The implementation of the Vedic mathematics and their application to the complex multiplier ensure substantial reduction of propagation delay in comparison with DA based architecture and parallel adder based implementation which are most commonly used architectures. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre using standard 90nm CMOS technology. The propagation delay of the resulting (16, 16)×(16, 16) complex multiplier is only 4ns and consume 6.5 mW power. We achieved almost 25% improvement in speed from earlier reported complex multipliers, e.g. parallel adder and DA based architectures.
81 citations