Delft University of Technology
A 6.3 μW 20 bit Incremental Zoom-ADC
with 6 ppm INL and 1 μV Offset
Chae, Youngcheol; Souri, Kamran; Makinwa, Kofi A.A.
DOI
10.1109/JSSC.2013.2278737
Publication date
2013
Document Version
Accepted author manuscript
Published in
IEEE Journal of Solid State Circuits
Citation (APA)
Chae, Y., Souri, K., & Makinwa, K. A. A. (2013). A 6.3 μW 20 bit Incremental Zoom-ADC with 6 ppm INL
and 1 μV Offset.
IEEE Journal of Solid State Circuits
,
48
(12), 3019-3027.
https://doi.org/10.1109/JSSC.2013.2278737
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JSSC Chae et al,
A 6.3W 20bit Incremental Zoom-ADC with 6ppm INL
and 1V Offset
Youngcheol Chae, Member, IEEE, Kamran Souri, Student Member, IEEE,
and Kofi A.A Makinwa, Fellow, IEEE
Y. Chae is with the Department of Electrical and Electronic Engineering,
Yonsei University, Seoul, Korea (E-mail: ychae@yonsei.ac.kr)
K. Souri and K. A. A. Makinwa are with the Electronic Instrumentation Laboratory/DIMES,
Delft University of Technology, Delft, The Netherlands.
Abstract – A 20-bit incremental ADC for battery-powered sensor applications is presented. It
is based on an energy-efficient zoom ADC architecture, which employs a coarse 6-bit SAR
conversion followed by a fine 15-bit ΔΣ conversion. To further improve its energy efficiency,
the ADC employs integrators based on cascoded dynamic inverters for extra gain and PVT
tolerance. Dynamic error correction techniques such as auto-zeroing, chopping and dynamic
element matching are used to achieve both low offset and high linearity. Measurements show
that the ADC achieves 20-bit resolution, 6ppm INL and 1μV offset in a conversion time of
40ms, while drawing only 3.5μA current from a 1.8V supply. This corresponds to a state-of-
the-art figure-of-merit (FoM) of 182.7dB. The 0.35mm
2
chip was fabricated in a standard
0.16μm CMOS process.
Index Terms – A/D conversion, battery-powered sensors, low power circuits, incremental
ADC, zoom ADC, SAR ADC, delta-sigma ADC, inverter-based integrator, and dynamic error
correction techniques.
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JSSC Chae et al,
A 6.3W 20bit Incremental Zoom-ADC with 6ppm INL
and 1V Offset
I. INTRODUCTION
Instrumentation applications, such as the readout of bridge transducers and smart sensors,
require analog-to-digital converters (ADCs) with high absolute accuracy and linearity as well
as high resolution [1]–[3]. Since the signals of interest are typically near DC, such ADCs must
also be robust to offset and 1/f noise. However, fulfilling all these requirements often results
in ADCs with poor energy-efficiency and/or high power consumption, thus making them
unsuitable for use in battery-powered autonomous systems.
SAR converters can be very energy efficient (< 10fJ/conv-step) [4], [5], but component
mismatch typically limits their resolution to the 1214 bit level, although this can be extended
to the 18-bit level with the help of calibration and dithering [6]. Dual-slope and delta-sigma
(ΔΣ) ADCs are capable of achieving even higher resolution and so are widely used in
instrumentation applications. However, the resolution of a dual-slope ADC is linearly
proportional to their conversion time, making them relatively slow and resulting in poor
energy-efficiency [7]. In contrast, delta-sigma (ΔΣ) ADCs, by utilizing oversampling and
higher-order noise-shaping, are able to achieve high resolution in less time and so can achieve
better energy efficiency. In instrumentation applications [8]–[14], ΔΣ ADCs are usually
operated in incremental mode, in which they are first reset and then operated for a fixed
number of cycles.
For many applications, e.g. in smart sensors, first or second-order incremental ΔΣ ADC
are often used [9]–[10]. However, achieving high resolution still requires a relatively long
conversion time, resulting in poor energy-efficiency. Higher-order or multi-bit architectures
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JSSC Chae et al,
are faster, but reported implementations still only achieve moderate energy efficiency [2], [11],
[12]. Another alternative is the extended counting architecture, in which the residue of a
coarse incremental ΔΣ ADC is digitized by a fine Nyquist ADC [13], [14]. This two-step
architecture is more energy efficient, since the resolution requirements on the relatively slow
ΔΣ ADC are now relaxed, leading to a faster conversion. However, the overall linearity of the
ADC is limited by the linearity of the Nyquist ADC. A recent implementation [14], achieves
good energy-efficiency (160dB FoM) from a 1.8V supply, but only achieves 15-bit linearity.
This paper describes the design of an energy-efficient 20-bit incremental zoom ADC. It
employs an energy-efficient two-step architecture, in which a coarse SAR ADC is used in
conjunction with a fine incremental ΔΣ ADC. Initially, the SAR ADC makes a coarse
conversion with a low resolution e.g. 6-bit. In the succeeding fine conversion, this result is
used to adjust the references of the ADC so as to zoom into a small range around the input
signal. In contrast to conventional two-step ADC architectures, the fine converter of a zoom
ADC does not digitize the residue of the coarse converter, and so the accuracy of the
conversion depends exclusively on the accuracy of the fine converter. Moreover, zooming
relaxes the resolution requirement of the fine converter, which, in turn, results in shorter
conversion times and small internal signal swings, which can then be handled by simple and
energy-efficient amplifiers. In this work, inverter-based integrators are used. The ADC’s
performance is further improved by the use of dynamic error correction techniques, such as
dynamic element matching (DEM) for high linearity, and auto-zeroing and chopping for low
offset and 1/f noise. The zoom ADC is implemented in a standard 0.16μm CMOS process and
achieves 119.8dB SNR, 6ppm INL, and 1μV offset in a conversion time of 40ms, while
drawing only 3.5μA current from a 1.8V supply [15].
This paper is organized as follows: Section II describes the zoom ADC architecture, while
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JSSC Chae et al,
Section III addresses the fundamental limitations and trade-offs in the design of a 20-bit
incremental zoom ADC. Section IV discusses the implementation details, and Section V is
devoted to the experimental results. Finally, conclusions are presented in Section VI.
![Fig. 7. Effect of OTA’s DC gain and its nonlinearity (a) Proposed zoom ADC (b) 1b 3rd order incremental ADC [2].](/figures/fig-7-effect-of-otas-dc-gain-and-its-nonlinearity-a-proposed-yxc8f5z5.webp)